B. Tech Projects Supervised (include student name, title & semester/yr):
July 2005 to April 2006 ? G. Ram Kumar, K.Tamil selvan and A. Priyanga VLSI Realization of PDNN
with Simultaneous Per Learning Rule? July 2005 to April 2006 - R. C. Priyadharshini, M. PriyaSandhya,S. Priyanka and Sudhania V, Hardware Modeling of pulsed Neuron with PW Linear AF? July 2005 toApril 2006 P. Sathish, S. SaravanaBalaji and R. Vignesh, VLSI Imp of NN with On-chip PertLearning July 2006 to April 2007 Ammar, Binati and Sethu VLSI Realization of Genetically
Evolved Neural Networks
M. Tech Projects Supervised (include student name, title & semester/yr):
Third Sem - July 2006 to December 2007- I Phase Shaik Juneed Hardware Imp of Time MultiplexedNeural Network Third Sem - July 2006 to December 2007- I Phase SriKanth, VLSI Realization ofLearning Algorithm for Neural Network.
Publications / Patents
Pulse-Density Neurohardware with On-Chip Perturbation Learning International Journal on SCI pp.43-51, Oct 2006. VLSI Design of Perturbation Learning Algorithm for Pulsed Neural Networks
International Conference on Advanced Communication Systems pp. 135-140, Jan 10-12, 2007.
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