ME

Doing Ph.D

Title of theThesis    : Vision based hexagonal sampling
Advisor                  :  Dr.K.A Narayanankutty
Expected date         :Dec 2009
of completion

2005-ODD Semester (July – Dec, 2005) Courses Taught:

1.EC501 Digital system Design with HDLs,15 students, 4hrs
2.EC291 Devices and circuits lab (A batch),63 students,6 Hrs
3. EC291 Devices and circuits lab (B batch),63 students,6 Hrs


2006-EVEN Semester (Jan – May, 2006) Courses Taught:

1.CS652 Digital Image processing,15 students,4 Hrs
2.EC398 Digital Signal processing Lab,63 students,6 Hrs
3.ME103-Workshop practice,63 students,3 Hrs

2006-ODD Semester (July – Dec, 2006) Courses Taught:

1.EC211 Digital Design,40 students,4 Hrs
2.EC293 Digital Design lab,40 students,6 Hrs.

2007-EVEN Semester (Jan – May 2007) Courses Taught:

1.EC328 Image processing,45 students,4 Hrs
2.ME180 Workshop practice(ECE A batch),63 students,3 Hrs
3. ME180 Workshop practice(Polymer),63 students,3 Hrs

B. Tech Projects Supervised (include student name, title & semester/yr):

”Efficient Edge detection and object segmentation using Gabor filters”-April 2006 Student’s name:Deepak..D, Dhayanithy.M and Mahendran.G .

M. Tech Projects Supervised (include student name, title & semester/yr):

Hexagonal pixel grid modeling using cellular Array Architecture,June 2006 -Senthil Nayaki.M
(M.Tech VLSI)
VLSI architecture for Edge detection using Hexagonal sampling,2007-Mohamed Raffi (M.Tech VLSI)
VLSI architecture for Skeletenization using Hexagonal sampling,2007,Kiran Moganti (M.Tech VLSI)


Research projects


Proposal given for ISRO project - Title:SAIR (Synthetic Aperture Imaging Radiometers and Hexagonal image processing”.

Publications / Patents

1. Boundary contour system for Image edge enhancement and Dynamic compression”in the IEEE conference “ INDICON 2005” at IIT Madras,Chennai during 12th Dec 2005.The paper was published in IEEE proceedingsIEEE catalog No :05EX1212 pages (457-462).

2. “Hardware implementation of CNN”, International Conference on Intelligent Sensors and Information Processing(ICISIP) ,January 2005.The paper was published in IEEE proceedingsIEEE catalog No :05EX979 pages (320-325)3. “Hexagonal pixel grid modeling for Edge detection and Design of cellular architecture for binary image skeletonization in the IEEE conference “ INDICON 2006” during Sep 2006.

3. The project titled “Hexagonal Pixel Grid Modeling For Edge Detection And Image Skeletanization “ is selected for the final presentation in the Innovate design contest organized by Altera and BITS Pilani .The paper was presented on 14.04.2007.

Demos/ Products:

1.ALTERA FPGA kit was received free of cost from ALTERA as the project was selected for the final presentation in the Innovate design contest organized by Altera and BITS Pilani .

2.Python language software was downloaded and installed in M.Tech lab and Project students from M.Tech CVIP were motivated to work in Python language which is very useful for image processing.

3.Maple software was downloaded and we are trying to work in it.


Best paper awards received for three times in the National / International conferences .

1. Finance committee member for the technical symposium named AURA for two consecutive years.
2. Technical committee member in the DSP workshop conducted by ECE department.
3. Digital design lab Incharge.
4. Class advisor for 3rd year EIE (2004-2008 batch).
5. Project work review committee
6. Council member in ISTE chapter-Amrita
7. Mentor – Introduction to PIC Microcontroller & It’s Applications during 2005 – 2006
8. Member of finance committee, ECE Dept.