M.Tech - Indian Institute of technology, Madras.

2005-ODD Semester (July – Dec, 2005) Courses Taught:

Vth Sem MCA, CA322, Microprocessor, 60, 5 Hrs (Theory)
Vth Sem MCA, CA324, Microprocessor Lab, 60, 6 Hrs (Lab)
Vth Sem B.Tech (ECE), EC294, Microprocessor Lab, 65, 6 Hrs (Lab)

2006-EVEN Semester (Jan – May, 2006) Courses Taught:

IInd Sem M.Tech (VLSI Design), EC 704, Embedded Controller & DSP Architecture, 17, 5 Hrs(Theory)
IInd Sem M.Tech (CEN), Hardware Modeling using Verilog HDL, 30, 5 Hrs (Theory)
IVth Sem B.Tech (ECE), EC294, Microcontrollers & Interfacing Lab, 65, 5Hrs (Lab)

2006-ODD Semester (July – Dec, 2006) Courses Taught:

VIIth Sem B.Tech (ECE), EC431, Embedded Systems, 67, 5 Hrs(Theory)
IIIrd Sem M.Tech (VLSI Design), EC659, Testing of VLSI Circuits, 17, 5Hrs (Theory)
IIIrd Sem B.Tech (IT), EC293, Digital Design Lab, 65, 6 Hrs (Lab)

2007-EVEN Semester (Jan – May 2007) Courses Taught:

IInd Sem M.Tech (VLSI Design), EC704, Embedded Controller & DSP Architecture, 20, 5 Hrs(Theory)
IInd Sem B.Tech (ECE), EC 499, Project Phase II, 20, 6 Hrs
IInd Sem M.Tech (VLSI Design), EC658, Seminar, 20, 3 Hrs
IVth Sem B.Tech (ME), EC296, Electronics Lab, 67, 6Hrs (Lab)
IInd Sem M.Tech (VLSI Design), EC662 VLSI Design Laboratory II, 20, 3 Hrs (Lab)

AUTOMATED BI-WHEEL ROBOT FOR NAVIGATION ON PRE-DEFINED ROUTES

7th &8th Sem, 2006-2007
0110301146 SOBIN SUNNY
0110301157 N VISHNU PRASAD
0110401611 ABRAHAM P A

FPGA IMPLEMENTATION OF FIR FILTER BASED ON COMPUTATION SHARING

7th &8th Sem, 2006-2007
00110301113 GEORGE J. CHIRAMEL
00110301136 D. RAJ THILAK
00110301147 SOHAM DAS

GENERATION OF A SYNTHESIZED NETLIST FOR A FAST COMPUTING PLATFORM IN MAGMA

7th &8th Sem, 2006-2007
0110301050 SREEJESH. M
0110401603 SREEJITH. S

GENERATION OF SOFT IP CORE FOR CRYPTOGRAPHIC PROCESSOR

7th &8th Sem, 2006-2007
0110301117 JAYAKARTHICK S.
0110301129 PRADEEP G.V.
0110301150 SUGAN SHREYAS V.
0110301151 SURYA NARAYANAN K.N.

SYNTHESIS OF A GENETIC ALGORITHM ENGINE FOR AUTOMATIC TEST PATTERN GENERATION IN VLSI

7th &8th Sem, 2006-2007
0110301105 ANISHA MOHANAN
0110301131 PRASHANTH K.G.
0110301149 SRUTHI SREEDHARAN

SYNTHESIS OF A HARVARD ARCHITECTURE BASED PROCESSOR

7th &8th Sem, 2006-2007
0110301123 NANDHINI.R
0110301511 LAKSHMI.T
0110301513 NEETHU KRISHNAN.K

MOBILE BRAILLE DISPLAY TERMINAL
7th &8th Sem, 2006-2007
0110301119 JAYANTHI D

RTOS FOR PIC 18XX MICROCONTROLLER – PIC WORKS

7th &8th Sem, 2006-2007
0110301008 ARUNKUMAR.R
0110301026 KRISHNAMOORTHY.S
0110301029 LEOPRINCE.F

EFFICIENT FINITE FIELD DIGIT SERIAL MULTIPLIER ARCHITECTURE FOR ELLIPTICA CURVE CRYPTOGRAPHY

7th &8th Sem, 2006-2007
0110301503 GAURAV KUMAR

16. M. Tech Projects Supervised (include student name, title & semester/yr):
MINIMIZING THE NUMBER OF PATHS IN BDDS

3rd & 4th Sem, 2006 -2007
CB205VL001 ALLEN EAPACHEN

TECHNOLOGY MAPPING FOR LUT BASED FPGA IN LOW POWER DESIGNS USING HYBRID METHODOLOGY FOR SWITCHING ESTIMATION

3rd & 4th Sem, 2006 -2007
CB205VL011 RAGHU RAM T

POWER PC ON CHIP PERIPHERAL BUS MODELING

3rd & 4th Sem, 2006 -2007
CB205VL015 SHAIK JUNEED

MODELING OF SATA

3rd & 4th Sem, 2006 -2007
CB205VL018 SRIKANTH MELLACHERUVU

LOW POWER TECHNLOGY MAPPING FOR LUT BASED FPGA USING GENETIC ALGORITHM

3rd & 4th Sem, 2006 -2007
CB204VL0 MAYA THOMAS

TECHNOLOGY MAPPING FOR LUT BASED FPGAs USING ECONVERGENT ANALYSIS

3rd & 4th Sem, 2006 -2007
CB204VL0 JAYAKUMAR M

1. Class advisor of F Batch, 2007 – 2008 admission
2. University representative to Ranchi Centre, Amrita Engg Entrance Exam
3. Group leader for seat allotment, Batch A, Amrita Engg Counseling
4. Incharge of catering for workshop in Applications of Digital Signal Processing
5. Member, catering group for Alumni meet
6. Lab Incharge – VLSI Lab
7. Mentor – Introduction to PIC Microcontroller & It’s Applications during 2005 – 2006
8. Member of finance committee, ECE Dept.