Dr. Anand Ramachandran currently serves as Professor at Amrita Center for Wireless Networks and Applications (AmritaWNA).
Teaching Interests: Introduction to Computing, Logic/Digital Design, Computer Architecture, Embedded Systems, Algorithms, Future Architectures/Applications
UNIVERSITY OF TEXAS AT AUSTIN Austin, TX Ph.D., Electrical and Computer Engineering 2004 Advisor: Dr. Margarida F. Jacome Energy-Aware Embedded Media Processing: System Architecture and Energy Management Policies
UNIVERSITY OF TEXAS AT AUSTIN Austin, TX M.S., Electrical and Computer Engineering 1998
INDIAN INSTITUTE OF TECHNOLOGY Chennai, India B. Tech., Chemical Engineering 1995
INDUSTRY EXPERIENCE, INTEL CORP. (OCT 2004 – JAN 2013)
POWER ARCHITECT, VPG Supervisor: Micah Barany Apr 2011 – Jan 2013
Power Management (System Sleep State, PCIe Power Management) for Intel MIC Servers: Architected the Power Management for a new family of Server-On-A-Chip. Defined System Sleep States and PCIe Power Management States for MIC (Many-Integrated Cores) based servers.
TEAM LEAD, POST-Si POWER TEAM, ASDG Supervisor: Madhu Gumma, June 2009 – Mar 2011 Post-Si Power Validation, Characterization and Optimization of 3 Atom SOCs:
Led a team of 4-7 people on Post-Si system power measurements and validation of three Atom SystemsOn-a-Chip (SOC). Validated power features of these SOCs, characterized parts for binning, and conducted optimization studies in order to lower power.
DESIGN ENGINEER, POWER TEAM, DEG Supervisor: Guru Prasad , Nov 2006 – May 2009
Power Estimation & Bin-Split Analysis for High-Performance Processors:
Developed spreadsheet power models and bin-split models for estimating the power consumption of high-performance processors. The models were used to study power-performance tradeoffs at the architectural-level during the early stages of the processor development cycle.
TEAM LEAD, POWER TEAM, MPG, Supervisor: Madhu Gumma, Oct 2004 – Nov 2006
Runtime Power Estimation for Thermal Throttling of the Northbridge (MCH):
Developed a method to estimate the power consumption of the MCH at runtime, by monitoring the occurrence of key events on the chip. The power estimate was used for dynamic thermal throttling.
Power Modeling of Intel Graphics Cores:
Led a team of 4 staff members for developing a parameterized, scalable, architectural model for estimating the power consumption of the Intel Graphics cores. The model was used with activity traces originating from both cycle-accurate and RTL simulations and was used to study power-performance tradeoffs of next generation architectures during early design space exploration.
Research Experience Prior To Joinning INTEL (1998 – 2004)
GRADUATE RESEARCH ASSISTANT, Advisor: Dr. Margarida F. Jacome, 2000 – 2004
Energy-Aware Embedded Computing: We proposed a novel special-purpose data memory subsystem, called Xtream-Fit, aimed at achieving high energy-delay efficiency for streaming media applications. A key novelty of Xtream-Fit was that it exposed a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology. A second key contribution was the ability to achieve very high energy-delay efficiency through a synergistic combination of:
GRADUATE RESEARCH ASSISTANT, Advisor: Dr. Margarida F. Jacome , 1998 – 2000
Code Generation for Embedded Processors: We proposed a policy to minimize energy consumption
due to off-chip data transfers by minimizing the number of spills from registers to memory in straight line code. We argued, however, that schedules with minimum number of spills do not necessarily have minimum latency. Accordingly, we proposed a class of policies to explore tradeoffs between register assignments leading to low latency, versus those leading to low energy consumption and showed how they may be tuned to specific datapath characteristics.