Dr. Bibhu Datta Sahoo completed his B.Tech. degree in Electrical Engineering from the Indian Institute of Technology, Kharagpur in 1998. He pursued his M. S. from the University of Minnesota, Minneapolis in 2000. He received his Ph.D from the University of California, Los Angeles in 2009.

From 2000 to 2006, he was with DSP Microelectronics Group at Broadcom Corporation, Irvine, CA, where he designed analog and digital integrated circuits for signal processing applications. From December 2008 to February 2010, he was with another VLSI Design company, Maxlinear Inc., Carlsbad, in California, USA.. Between March and December of 2010, he was a Post Doctoral Research Scholar at Communication Circuits Laboratory, UCLA. After serving as an Assistant Professor at IIT Kharagpur in the year 2011, he joined Amrita as an Associate Professor in the Department of ECE on December 21, 2011. He has several publications in International Journals and Conferences of repute and has two US patents to his credit. His research interests include data conversion, signal processing, analog and digital circuit design. He received the 2008 Analog Devices Outstanding Student Designer Award.


Publication Type: Conference Paper
Year of Publication Publication Type Title
2016 Conference Paper A. T. Kunnath and Sahoo, B. Datta, “A Digitally Assisted Radiation Hardened Current Steering DAC”, in Proceedings of the IEEE International Conference on VLSI Design, 2016, vol. 2016-March, pp. 559-560.[Abstract]

This paper studies the effect of radiation on the performance of a 12-bit current steering digital-to-analog converter (DAC) and proposes a digitally assisted radiation hardening technique to overcome the performance degradation due to radiation. Circuit level simulations in UMC 65-nm SP process show that Signal-to-Noise Ratio (SNR) of the DAC falls from 74 dB to 41. 29 dB with radiation dose ranging from 0 to 100 Mrad and the proposed hardening technique overcomes this performance degradation. © 2016 IEEE.

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2015 Conference Paper T. Rahul, Sahoo, B. Datta, Arya, S., Parvathy, S. J., and Vulligaddala, V. B., “A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application”, in Proceedings of the IEEE International Conference on VLSI Design, 2015, vol. 2015-February, pp. 265-270.[Abstract]

This paper proposes a wide dynamic-range low-power signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency. However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slew rate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA. © 2015 IEEE.

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2015 Conference Paper C. Ravi, Sarma, V., and Sahoo, B. Datta, “At speed digital gain error calibration of pipelined ADCs”, in Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 2015.[Abstract]

This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with resistor ladder. The proposed technique also facilitates the calibration to happen at full speed overcoming the drawbacks of existing foreground calibration techniques. 12-bit ADCs with first stage resolution of 1.5-bit, 2.5-bit, 3.5-bit, and 2-bit, followed by an ideal back-end ADC were simulated in system level using MATLAB and then at circuit level in Cadence. The circuit simulations incorporate various non-idealities like finite op-amp gain, op amp settling, and capacitor mismatch. Circuit level simulations in Global Foundry's (GF) 55-nm process with an an open loop op amp gain of 50 dB and capacitor mismatch of ±3% show that the calibration method improves the SFDR by more than 30 dB and SNDR by more than 25 dB. © 2015 IEEE.

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2009 Conference Paper B. Datta Sahoo and Razavi, B., “A fast simulator for Pipelined A/D Converters”, in Circuits and Systems, 2009. MWSCAS'09. 52nd IEEE International Midwest Symposium on, 2009.[Abstract]

A simulator for comprehensive analysis of pipelined A/D converters has been developed in MATLAB and compiled to an executable that can be run on various platforms. The simulator accepts user-specified parameters such as resolution per stage, number of stages, input and clock frequencies, input amplitude, op amp nonlinearity, capacitor mismatch, comparator offset, and clock jitter. The tool then provides the simulated performance in the form of residue plots, differential and integral nonlinearity profiles, output spectrum, and input-referred thermal noise. Compared with Cadence's Spectre, the proposed simulator runs several orders of magnitude faster while incurring a small error. More »»
2009 Conference Paper B. Datta Sahoo and Razavi, B., “U-PAS: A user-friendly ADC simulator for courses on analog design”, in Microelectronic Systems Education, 2009. MSE'09. IEEE International Conference on, 2009.[Abstract]

A simulator with a graphical user interface has been developed for the analysis and design of pipelined analog-to-digital converters. The user can enter parameters such as resolution per stage, number of pipelined stages, input and clock frequencies, input amplitude, op amp nonlinearity, capacitor mismatch, and comparator offset. The simulator then computes various static and dynamic properties of the system such as residue plots, differential and integral nonlinearity profiles, output spectrum, and input-referred noise. Available as an executable code, the simulator can run on various platforms. More »»
Publication Type: Journal Article
Year of Publication Publication Type Title
2016 Journal Article B. Datta Sahoo and Inamdar, Ab, “Thermal-Noise-Canceling Switched-Capacitor Circuit”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 628-632, 2016.[Abstract]

Thermal noise has been a fundamental bottleneck in building high dynamic range switched capacitor (SC) circuits. This brief proposes an SC thermal-noise-canceling circuit. The technique, demonstrated using a unity-gain sample-and-hold amplifier (SHA) in IBM 32-nm silicon-on-insulator (SOI) process, gives 5.0-, 4.4-, and 3.7-dB improvements while operating at 100, 250, and 500 MHz, respectively, and consuming only 30% additional power as compared to 400% to get a similar improvement without noise cancelation. More »»
2009 Journal Article B. Datta Sahoo and Razavi, B., “A 12-Bit 200-MHz CMOS ADC”, Solid-State Circuits, IEEE Journal of, vol. 44, pp. 2366–2380, 2009.[Abstract]

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply. More »»
2003 Journal Article B. Datta Sahoo and Parhi, K. K., “A low power correlator for CDMA wireless systems”, Journal of VLSI signal processing systems for signal, image and video technology, vol. 35, pp. 105–112, 2003.[Abstract]

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range −7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5 μ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design. More »»
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