Dr. M. Nirmala Devi obtained her B.E. degree in Electronics and Communication Engineering (ECE) in 1990 and M. E. (Applied Electronics) Degree in 1996 from Government College of Technology, Coimbatore, Bharathiar University. She is currently working as the Professor in Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. During her tenure at Amrita, she received her Ph. D. degree in the area of VLSI Design of Artificial Neural Networks from Anna University, Chennai in 2010. She has been the coordinator for M. Tech. VLSI Design program.

She has delivered invited lectures on VLSI Design in AICTE and UGC sponsored faculty development programs and conferences. She has also organized a few in-house workshops on “Analog and Digital VLSI Designs and tools”. Moreover she has organized the “National Symposium on Green Electronics” during December 2014. She has served as Board of Studies member for some institutions. She is the recipient of “Appreciation Award” from Amrita Institute of Technology during the year 2003. Moreover, Marquis Who’s Who in the World 2011 distinguishes her as one of the leading achievers from around the country. Furthermore, International Biographical Centre, Cambridge, England has chosen her for inclusion in the prestigious publication “2000 Outstanding Intellectuals of the 21st Century – 2011”. Her areas of interest include VLSI Design and Testing, Computational Intelligence, Hardware Security and Trust, Evolvable Hardware and RF CMOS System Design. She has published around 55 papers in the International Journals and Conferences in her field of expertise. She has served as the reviewer for international conferences and international journals which include the following;

  1. Springer Journal of the Institution of Engineers (India): Series B
  2. Inderscience Int. Journal of Information and Communication Technology


  • Appreciation Award - Amrita Institute of Technology & Science- 2003
  • Marquis Who’s Who in the World- 2011
  • 2000 Outstanding Intellectuals of the 21st Century- 2011 - International Biographical Center, Cambridge, England.

Major Research Objectives

  • VLSI Design & Testing- Development of efficient algorithms for VLSI testing and extending it to focus on low power concept with compression schemes
  • RF CMOS System design- Application of CMOS or GaN technology in the design of RF transceiver systems at L, S, and C bands
  • Hardware Security & Trust- Enhancing the security of VLSI chips in safety critical applications like missiles & biomedical implants
  • Computational Intelligence- Application the high potential intelligence concepts like Neural networks, Particle Swarm Optimization, Genetic Algorithms etc., on social and health related problems like perception engineering & cancer Diagnosis for the improvement
  • Evolvable Hardware- Emulation of efficient and optimized algorithms on FPGAs to develop proof-of-concept.

PhD Program and Area of Focus

  1. Secured testing of VLSI Circuits
  2. VLSI Testing and Security
  3. Design for Security
  4. Antenna Design & Optimization
  5. Hardware Design for Trust
  6. Security in Multi-core Architectures
  7. RF CMOS Design of Low-noise Amplifier

Funded Projects

Title of the Research proposal- Hardware Trojan Detection and Consistency based Diagnosis

Investigators- Dr. Nirmala Devi M., Dr. Jayakumar M., Mohankumar N., Dr. Sethumadhavan M.

Funding Agency- DRDO, New Delhi

Period- Two Years

UG/PG Publications

  1. FPGA Implementation of Genetically Evolved Artificial Neural Networks For Effective Resource Utilization
  2. A Power Aware Reordering Based Compression Scheme for Test Volume Reduction
  3. Power Reduction and Defect Coverage Improvement in At-Speed Testing
  4. VLSI Realization of fault tolerant Artificial Neural Networks
  5. FPGA Implementation of Feedforward Neural Network with Layer Multiplexing
  6. Improved Particle Swarm Optimization
  7. Security Enhanced Testing Using Scrambling and Test Compression
  8. Modified PSO with Adaptive Local Search
  9. Test Compression for Low-power Testing
  10. Small-signal Modelling of GaN HEMT based Transistor using PSO
  11. Multi-objective PSO
  12. Design of RF CMOS LNA for Millimeter wave Technology


Publication Type: Journal Article
Year of Conference Publication Type Title
2015 Journal Article R. Bhakthavatchalu and M. Nirmala Devi, “Deterministic seed selection and pattern reduction in logic BIST”, International Journal of Applied Engineering Research, vol. 10, pp. 7537-7551, 2015.[Abstract]

<p>A technique to select the proper seed and to reduce the number of test patterns generated in Logic Built in Self Test (BIST) is proposed. This paper explains the algorithm that can be used offline of BIST flow to search and classify the random patterns based on the deterministic test patterns generated by the Automatic Test Pattern Generator (ATPG). The seed activated Linear Feedback Shift Register (LFSR) generates exhaustive test patterns which are applied on any Circuit Under Test (CUT). The responses are received at the output of the scan chains in the CUT and they are compressed to produce a signature. This signature is compared with the expected golden signature to indicate the BIST status. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns compared to an arbitrary seed. This technique is well suited for any scan based sequential design. It is applied on ISCAS-89 designs with the help of Cadence Encounter Test Architect 13.1 tool. The results show that this method is comparable with similar methods. Possible limitations of this technique when employed in large designs and solutions are also suggested as future work. © Research India Publications.</p>

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2015 Journal Article K. Balamurugan, M. Nirmala Devi, and Jayakumar, M., “Performance analysis of 60 GHZ low noise amplifiers using multi-gate mosfets”, Journal of Theoretical and Applied Information Technology, vol. 77, pp. 373-381, 2015.[Abstract]

Short-channel devices are preferred for realizing millimetre circuits, but these are affected by the short- channel effects (SCE). Multi-Gate (MG) MOSFET is found to be an alternative to overcome this drawback. In this paper, study and analysis of DC and AC parameters of MG MOSFETs have been attempted and small signal gain (y21) of multi-gate structure is analytically derived. Design of low noise amplifier (LNA) at 60 GHz using the channel charging resistance model has been done.Small signal gain and noise figure using the channel charging resistance model has been derived and analysed. The proposed LNA circuit uses various multi-gate MOSFET structures and the results are compared with conventional MOSFET based design. The designed LNA using a Quadruple Gate structure exhibited the noise figure improvement of 24.4% and 42.79% when operated at 1 V and 1.5 V respectively. Also the corresponding gain increases by 2.38 times and 4.9 times compared with conventional single gate MOSFET design. © 2005 - 2015 JATIT &amp; LLS. All rights reserved.

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2015 Journal Article R. Bhakthavatchalu, Kannan, S. K., and M. Nirmala Devi, “Verilog design of programmable JTAG controller for digital VLSI IC's”, Indian Journal of Science and Technology, vol. 8, 2015.[Abstract]

The objective of this work is to design and implement a custom reconfigurable JTAG controller in Verilog. It can be directly inserted in to a new digital IC designs with little modifications. It is fully compatible with IEEE 1149.1 standards. Additional programmable private instructions can also be added in to the design. A secure access mechanism is provided in to the controller which helps in protecting the system by preventing the un-authorized users from interfering with the system functions. A locking and opening mechanism and a password key based access control were incorporated as part of the JTAG controller module. The controller was configured to fit into different ISCAS'89 digital VLSI benchmark designs and results are analysed. It is observed that as the design size increases the area and power overhead decreases but the number of boundary scan vectors increases. All the designs were written in Verilog and RTL simulations were performed using Cadence NC-Sim Simulator. Cadence Encounter Test Architect 13.1 was used to check the boundary scan flow and analysis. A line graph to depict the power and area overhead is also shown. Complete performance analysis of the ISCAS'89 designs with and without the JTAG controller was performed. The power and area overhead was found to be negligible as the size of the VLSI designs increases.

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2015 Journal Article R. Bhakthavatchalu and M. Nirmala Devi, “Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture”, International Journal of Engineering and Technology, vol. 7, no. 3, pp. 973-984, 2015.[Abstract]

A technique to provide programmable secure access to the scan based Logic Built in Self- Test (BIST) structures is proposed. Joint Test Access Group (JTAG) interface is the major test access method used in VLSI IC’s. At the same time, it can be misused as a means to access and hack the hardware circuitry of the IC. It is addressed in this method to prevent unauthorized users from hacking the JTAG interface and interfering in the Logic BIST test functions. A two stage, multiple crypto algorithms based separate authorization schemes are used. A configuration register can be programmed to select the level of security to a specific user group. Different crypto algorithms can be chosen, with user specifiable key lengths. A challenge response protocol is employed to authenticate the user and corresponding accessibility. All the features included are compliant with the IEEE JTAG standard 1149.1. This technique is applied on ISCAS-89 and ISCAS-99 benchmark designs with the help of Cadence Encounter true time 13.1 design automation tools and results are shown. A small amount of (less than 2 to 5%) increase in area reported for implementing the security features.

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2015 Journal Article R. Lavanya, Nagarajan, N., and M. Nirmala Devi, “Computer-aided Diagnosis of Breast Cancer by Hybrid Fusion of Ultrasound and Mammogram Features”, Advances in Intelligent Systems and Computing, vol. 325, pp. 403–409, 2015.[Abstract]

Ultrasound images are increasingly being used as an important adjunct to X-ray mammograms for diagnosis of breast cancer. In this paper, a computer-aided diagnosis system that utilizes a hybrid fusion strategy based on canonical correlation analysis (CCA) is proposed for discriminating benign and malignant masses. The system combines information from three different sources, i.e., ultrasound and two views of mammogram, namely, mediolateral oblique (MLO) and craniocaudal (CC) views. CCA is employed on ultrasound-MLO and ultrasound-CC feature pairs to explore the hidden correlations between ultrasound and mammographic view. The two pairs of canonical variates are fused at the feature level and given as input to support vector machine (SVM) classifiers. Finally, decisions of the two classifiers are fused. Results show that the proposed system outperforms unimodal systems and state-of-the-art fusion strategies.

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2015 Journal Article A. Indoria, Varrun, V., Reddy, M. Krishna, Sathyasai, T., Anand, B., and M. Nirmala Devi, “State Variable Filter Design Using Improvised Particle Swarm Optimization Algorithm”, Advances in Intelligent Computing and Systems (AISC) series, vol. 325, pp. 71–78, 2015.[Abstract]

State variable filter design using particle swarm optimization algorithm proves to be better when compared to the conventional design method. It gives several solutions to the component values which are useful in designing the state variable filter. The automatic termination technique gives the best possible solution in lesser time. This technique has several advantages in terms of a quicker convergence rate and efficient computation toward the suitable output, where an added advantage gives the user a control over the output’s precision. The performance parameter here can be defined as the trade-off between the convergence time and accuracy of the resulting solution, which is determined by the precision value. The results also indicate that the solution with a predefined precision level can be obtained with the minimum number of iterations in minimum time. © Springer India 2015.

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2014 Journal Article K. Balamurugan, M. Nirmala Devi, and Jayakumar, M., “Design of V-band low noise amplifier using current reuse topologies”, International Journal of Applied Engineering Research, vol. 9, pp. 27319-27330, 2014.[Abstract]

This paper presents the design of single stage, cascode Low Noise Amplifier (LNA) at V-band using current reuse topologies. First, the design of source inductor and gate inductor of cascode transistor are done by considering its small signal equivalents. For this, the output resistance, the internode resistance, the terminal and the gate-source capacitances of cascode amplifier are considered and exploited to determine the value of source and gate inductance. This results in compact and efficient LNA design. Compared to the conventional cascode design, the forward gains at 60 GHz using current reuse source inductor, gate inductor and its combination increases by 8.71%, 52.7% and 64.6% respectively. In second part, the proposed work describes the LNA circuit that uses the design of inductive load thereby achieving reduced VDD supply at common gate transistor. The forward gain and noise figure obtained from this method are 5.8 dB and 2.3 dB respectively. Power consumption of LNA design having inductive load is 7.43 mW that is comparatively lower than the conventional cascode design, which consumes 8.11 mW. For the two designs, IIP3 obtained are -3 dBm and -1 dBm respectively and found to be in good agreement with the expected response. © Research India Publications.

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2012 Journal Article P. R. Sruthi and M. Nirmala Devi, “A modified scheme for simultaneous reduction of test data volume and testing power”, Sixteenth International Symposium on VLSI Design and Test (VDAT 2012, vol. 7373 LNCS, pp. 198-208, 2012.[Abstract]

Today's electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS'89 benchmark circuits. © 2012 Springer-Verlag.

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2010 Journal Article M. Nirmala Devi and Arumugam, S., “VLSI implementation of artificial neural networks - A survey”, International Journal of Modelling and Simulation, vol. 30, pp. 148-154, 2010.[Abstract]

Artificial neural networks (ANNs) are simplified models of human brain. These are networks of computing elements that have the ability to respond to input stimuli and generate the corresponding output. To obtain a desirable output, the network weights must be trained upon the available data many times. Hence the software realization of ANN takes many hours to learn a particular example. On the other hand, neural network (NN) in hardware can speed up the training by several orders of magnitude, due to the faster nature of the hardware. Different types of VLSI implementation of ANN are found in the literature. This paper provides a brief survey of digital and pulsed neurohardware. It highlights the important issues related and shows the possible direction of future research.

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2009 Journal Article M. Nirmala Devi, Mohankumar, N., and Arumugam, S., “Modeling and analysis of neuro–genetic hybrid system on FPGA”, Elektronika ir Elektrotechnika (International Journal of Electrical and Electronics Engineering (JEEE)), vol. 96, pp. 69-74, 2009.[Abstract]

Simultaneous evolution of the architecture and adaptation of weights of an Artificial Neural Network is executed using Genetic Algorithm (GA) to overcome the local minima problem. Absence of learning unit simplifies the Very Large Scale Integration (VLSI) realization of evolved Neural Network (NN). Potential of the Neurohardware is tested on two benchmark circuits; Eight-bit even Parity function and nine-bit Character Recognition. Binary input facilitates the use of comparators instead of multipliers in the hidden layer neuron, reducing the hardware complexity. While evolving the parity function using GA, the number of hidden layer neuron is reduced to half, which in turn reduces the silicon area appreciably. Character Recognition Network converges faster with acceptable error. Simulated results ensure that the designed Neuro-Genetic Hybrid System is not only fast and accurate but also hardware friendly.

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Publication Type: Conference Paper
Year of Conference Publication Type Title
2014 Conference Paper R. Bhakthavatchalu, Krishnan, S., Vineeth, V., and M. Nirmala Devi, “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.[Abstract]

A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented. This technique uses an offline algorithm to search and classify the random patterns based on the deterministic test patterns generated by the automatic test pattern generator (ATPG). The seed activated linear feedback shift register (LFSR) generates exhaustive test patterns which are applied on any design under test (DUT). The responses are received at the output of the scan chains in the DUT and they are compressed to produce a signature. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns than an arbitrary seed. Also, this technique helps to estimate the number of BIST test patterns to be generated to achieve specific fault coverage. Results on six ISCAS-89 designs with the help of Cadence Encounter true time 13.1 ATPG is shown. © 2014 IEEE.

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2014 Conference Paper B. Anand, Aakash, I., ,, Varrun, V., Reddy, M. K., Sathyasai, T., and M. Nirmala Devi, “Improvisation of particle swarm optimization algorithm”, in 2014 International Conference on Signal Processing and Integrated Networks, SPIN 2014, Noida, 2014, pp. 20-24.[Abstract]

The improvised Particle Swarm Optimization (PSO) Algorithm offers better search efficiency than conventional PSO algorithm. It provides an efficient technique to obtain the best optimized result in the search space. This algorithm ensures a faster rate of convergence to the desired solution whose precision can be preset by the user. The inertia parameter is varied linearly with iteration number, which results in more accurate solution for unimodal functions. The control over the precision value acts as a trade-off between the convergence time and precision of the desired solution, and it can be viewed as a performance parameter. Swarm convergence is followed by a mutation process, which further improves the obtained result by enhancing the local search ability of some particles. The results show that the solution with predefined precision level can be obtained with the minimum number of iterations. © 2014 IEEE.

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2014 Conference Paper S. Sarathkrishna, Balamurugan, K., M. Nirmala Devi, and Jayakumar, M., “Design and analysis of GaN HEMT based LNA with CPW matching”, in 2014 Eleventh International Conference on Wireless and Optical Communications Networks (WOCN), , 2014.[Abstract]

GaN based devices are in great demand due to its rugged characteristics at extreme conditions. In this paper, design of GaN monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with coplanar waveguide matching is presented to understand the key aspects of high gain, low noise figure and high linearity. The LNA can be used in base station technologies as frequency of interest is from 0.6-3 GHz. It delivers gain of 23 dB and noise figure 0.3 dB and OIP3 upto 51 dBm. The linear performance presented here enables reconfigurable designs of LNA over multiple octaves of bandwidth.

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2012 Conference Paper P. R. Sruthi and M. Nirmala Devi, “Modified AVR Code for Test Data Compression”, in 7th International Workshop on Unique Chips and Systems (UCAS-7) in conjunction with 18th International Symposium on High Performance Computer Architecture, IEEE Computer Society, New Orleans, Louisiana, USA, 2012.
2011 Conference Paper A. Scaria, D. Nath, B., M. Nirmala Devi, and Mohankumar, N., “Hardware implementation of svd based colour image watermarking in wavelet domain”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]

While it has become very easy to process and store digital images effectively, it has also paved way for ease in illegal production and redistribution. Watermarking is the best way to protect digital image against illegal recording and distribution. From the literature survey, it has been affirmed that the frequency domain techniques are more robust than spatial domain techniques. In this paper a singular value decomposition (SVD) based watermarking is executed in wavelet domain. This paper proposes the design and hardware implementation of a fast RGB to YUV converter by standard NTSC conversion and reconstruction formulae using optimal 2-D systolic arrays for matrix multiplication.The scheme have been implemented in Altera Cyclone II FPGA. The hardware implementation of 2D DWT decomposition and IDWT reconstruction were implemented in Xilinx xc3s1000-4fg320. Watermarks inserted in the lowest frequencies (LL subband) are resistant to certain group of attacks, and watermarks embedded in highest frequencies (HH subband) are resistant to another group of attacks. Embedding the same watermark in all 4 blocks, will make it extremely difficult to remove or destroy the watermark from all frequency subbands. The proposed algorithm is less resilient to geometric distortion including rotation, scaling and translation. The hardware implementation watermarking schemes has advantages over the software implementation in terms of high performance, and reliability. A hybrid SVD image watermarking in wavelet domain, will have more robustness. © 2011 IEEE. More »»
Publication Type: Conference Proceedings
Year of Conference Publication Type Title
2014 Conference Proceedings B. S. Mahalakshmi, Manikantan, S., Bhavana, P., Prem, A. M., SaiEknaath, R. S. S., and M. Nirmala Devi, “Small signal modelling of GaN HEMT at 70GHz”, International Conference on Signal Processing and Integrated Networks (SPIN), 2014 . IEEE, Noida, Delhi-NCR, India, pp. 739 - 743, 2014.[Abstract]

A new 18-element small-signal model for GaN high electron mobility transistor is presented to operate at very high frequencies around 70 GHz. This model accounts for the need of a capacitor to represent the capacitive effect between the end of the drain electrode and contacting pad of the gate electrode. An extrinsic parasitic gate-drain capacitance as for higher frequencies this parameter becomes significant even under cold-FET conditions. This novel approach compensates for the high linear dependency of inductance at such high frequencies and the improved performance is evident in the S-parameter modelled. The validity of the proposed model has been well-illustrated up to 100 GHz frequency by the modelled S-parameters.

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2014 Conference Proceedings J. Sirisha, C., N. Vaishnavi, P., N. K., S., S. Vidhya, G., Y., Balamurugan, K., M. Nirmala Devi, and M., J., “Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, pp. 1-8, 2014.[Abstract]

A new flexible logic Built in Self-Test (BIST) scheme that has complete reconfigurability is presented. This technique uses a Linear Feedback Shift Register (LFSR), Multiple Input Signature Register (MISR) and a Bist controller; all of them programmable to work with any scan based design and targeted to detect all possible single stuck at faults. The seed activated LFSR generates exhaustive test patterns which are applied on any Design Under Test (DUT) and responses are received at the output of the scan chains in the DUT and the responses are compressed to produce a signature. It is shown that this scheme works with multiple designs without any structural modification in the BIST blocks. This technique is well suited to work with any scan based sequential design. A maximum number of 100 scan chains supported which can be increased. It eliminates the drawback of creating new bist logic for different blocks of a single System on Chip (SoC). Parallel testing of different blocks within a SoC is also possible within the power limits. The Reconfigurable Logic BIST (RLBIST) is checked in six designs and techniques are adopted to optimize the testpatterns with the help of cadence Encounter true time 13.1 ATPG. It is shown that the speed, power and area of the DUT are not affected by the reconfigurable BIST structures.

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2014 Conference Proceedings R. Bhakthavatchalu, M. Nirmala Devi, and Krishnan, S., “Reconfigurable Logic Built in Self-Test technique for SoC Applications”, International Conference on Communication and Computing, ICC 2014, vol. 3. Elsevier, Bangalore, India, pp. 16-23, 2014.
2014 Conference Proceedings P. Sankar and M. Nirmala Devi, “Particle Swarm Optimization with Different Modifications”, Third International Conference on Recent Trends in Engineering and Technology. Elsevier Science and Technology, Chanwad, pp. 551-556, 2014.
2014 Conference Proceedings M. Vijitha and M. Nirmala Devi, “Test data Volume Reduction Using Compressed Scan Mode Architecture”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, 2014.
2013 Conference Proceedings G. Srujana, Radhika, S., Sonu, S., T. Sai, V., Tharun, V., and M. Nirmala Devi, “Improved Particle Swarm Optimisation with Modified Velocity Calculation”, IEEE Workshop on Computational Intelligence: Theories, Applications and Future Directions. Institute of Technology (IIT), Kanpur, pp. 108-113, 2013.
2011 Conference Proceedings Na Haridas and M. Nirmala Devi, “Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST”, ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, vol. 1. Kanyakumari, pp. 350-354, 2011.[Abstract]

Pattern generation is the most important module in a BIST. Out of many test pattern generators (TPG) explored for BIST, linear feedback shift registers (LFSR) are widely used due to their ability to produce highly random patterns. Various improvements over the basic forms of LFSR are available. In the current study, the selection of an appropriate LFSR for a given benchmark circuit is analyzed. It is done by considering various factors such as selection of characteristic polynomial and seed to obtain high fault coverage, minimize invalid patterns, area overhead and time taken to generate the patterns. © 2011 IEEE.

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2011 Conference Proceedings N. Mohankumar, M. Nirmala Devi, D. Nath, B., and Scaria, A., “VLSI architecture for compressed domain video watermarking”, First International Workshop on Peer-to-Peer Networks and Trust Management, vol. 205 CCIS. Springer in Communications in Computer and Information Science (CCIS) Series, Chennai, India, pp. 405-416, 2011.[Abstract]

Digital watermarking has become very important for protecting the authenticity of multimedia objects as they become easier to copy, exchange, and modify due to the large diffusion of powerful personal computers. The video has been utilized in a variety of applications such as video editing, Internet video distribution, wireless video communications etc. Some of these applications are likely to get great benefit from video watermarking technology. Main objective of this research is to design robust perceptual video watermarking targeted at achieving better performance and reliability. Due to its robust nature, Discrete Cosine Transform (DCT) watermarking was chosen in this work to accomplish video copyright protection. The watermark is inserted in the video stream during compression, resulting in an optimized compression/watermarking algorithm and system.

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2008 Conference Proceedings Va Saichand, M. Nirmala Devi, Arumugam, Sc, and Mohankumar, Nd, “FPGA realization of activation function for artificial neural networks”, IEEE 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, vol. 3. IEEE, Taiwan, pp. 159-164, 2008.[Abstract]

Implementation of Artificial Neural network (ANN) in hardware is needed to fully utilize the inherent parallelism. Presented work focuses on the configuration of Field-Programmable Gate Array (FPGA) to realize the activation function utilized in ANN. The computation of a nonlinear activation function (AF) is one of the factors that constraint the area or the computation time. The most popular AF is the log-sigmoid function, which has different possibilities of realizing in digital hardware. Equation approximation, Lookup Table (LUT) based approach and Piecewise Linear Approximation (PWL) are a few to mention. A two-fold approach to optimize the resource requirement is presented here. Primarily, Fixed-point computation (FXP) that needs minimal hardware, as against floating-point computation (FLP) is followed. Secondly, the PWL approximation of AF with more precision is proved to consume lesser Si area when compared to LUT based AF. Experimental results are presented for computation. © 2008 IEEE.

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Reviewer and Program Committee Member

  1. Reviewer - Springer Journal of the Institution of Engineers (India): Series B
  2. Reviewer - Inderscience International Journal of Information and Communication Technology
  3. Reviewer for the International Conference- VLSI- SATA- 2015, 2016.
  4. Reviewer & PC member- International Symposium- VDAT- 2015
  5. Reviewer for the International Journal- Advances in Electrical and Electronic Engineering, VSB- Technical University of Ostrava, Czech Republic, 2014.
  6. Program committee member & Reviewer of "International Conference on Education (EDU 2014)" to be held in Bangalore, INDIA, 2014.
  7. Reviewer for the Journal of The Institution of Engineers (India): Series B, India in 2014.
  8. Reviewer for the International Conference on Embedded Systems ICES 2014, July 3- 5, 2014, Dept. of EEE, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, 2014.
  9. Program committee member & Reviewer of "The Third International conference on Parallel, Distributed Computing and Applications (IPDCA - 2014)" to be held in Chennai,India.
  10. Member of the editorial board- Chrome Publishing Group, Noida, NCR Delhi, 2014.
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