Dr. Nirmala Devi M.
Dr. M. Nirmala Devi obtained her B.E. degree in Electronics and Communication Engineering (ECE) in 1990 and M. E. (Applied Electronics) Degree in 1996 from Government College of Technology, Coimbatore, Bharathiar University. She is currently working as the Professor in Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. During her tenure at Amrita, she received her Ph. D. degree in the area of VLSI Design of Artificial Neural Networks from Anna University, Chennai in 2010. She has been the coordinator for M. Tech. VLSI Design program.
She has delivered invited lectures on VLSI Design in AICTE and UGC sponsored faculty development programs and conferences. She has also organized a few in-house workshops on “Analog and Digital VLSI Designs and tools”. Moreover she has organized the “National Symposium on Green Electronics” during December 2014. She has served as Board of Studies member for some institutions. She is the recipient of “Appreciation Award” from Amrita Institute of Technology during the year 2003. Moreover, Marquis Who’s Who in the World 2011 distinguishes her as one of the leading achievers from around the country. Furthermore, International Biographical Centre, Cambridge, England has chosen her for inclusion in the prestigious publication “2000 Outstanding Intellectuals of the 21st Century – 2011”. Her areas of interest include VLSI Design and Testing, Computational Intelligence, Hardware Security and Trust, Evolvable Hardware and RF CMOS System Design. She has published around 55 papers in the International Journals and Conferences in her field of expertise. She has served as the reviewer for international conferences and international journals which include the following;
- Springer Journal of the Institution of Engineers (India): Series B
- Inderscience Int. Journal of Information and Communication Technology
- Appreciation Award - Amrita Institute of Technology & Science- 2003
- Marquis Who’s Who in the World- 2011
- 2000 Outstanding Intellectuals of the 21st Century- 2011 - International Biographical Center, Cambridge, England.
Major Research Objectives
- VLSI Design & Testing- Development of efficient algorithms for VLSI testing and extending it to focus on low power concept with compression schemes
- RF CMOS System design- Application of CMOS or GaN technology in the design of RF transceiver systems at L, S, and C bands
- Hardware Security & Trust- Enhancing the security of VLSI chips in safety critical applications like missiles & biomedical implants
- Computational Intelligence- Application the high potential intelligence concepts like Neural networks, Particle Swarm Optimization, Genetic Algorithms etc., on social and health related problems like perception engineering & cancer Diagnosis for the improvement
- Evolvable Hardware- Emulation of efficient and optimized algorithms on FPGAs to develop proof-of-concept.
PhD Program and Area of Focus
- Secured testing of VLSI Circuits
- VLSI Testing and Security
- Design for Security
- Antenna Design & Optimization
- Hardware Design for Trust
- Security in Multi-core Architectures
- RF CMOS Design of Low-noise Amplifier
Title of the Research proposal- Hardware Trojan Detection and Consistency based Diagnosis
Investigators- Dr. Nirmala Devi M., Dr. Jayakumar M., Mohankumar N., Dr. Sethumadhavan M.
Funding Agency- DRDO, New Delhi
Period- Two Years
- FPGA Implementation of Genetically Evolved Artificial Neural Networks For Effective Resource Utilization
- A Power Aware Reordering Based Compression Scheme for Test Volume Reduction
- Power Reduction and Defect Coverage Improvement in At-Speed Testing
- VLSI Realization of fault tolerant Artificial Neural Networks
- FPGA Implementation of Feedforward Neural Network with Layer Multiplexing
- Improved Particle Swarm Optimization
- Security Enhanced Testing Using Scrambling and Test Compression
- Modified PSO with Adaptive Local Search
- Test Compression for Low-power Testing
- Small-signal Modelling of GaN HEMT based Transistor using PSO
- Multi-objective PSO
- Design of RF CMOS LNA for Millimeter wave Technology
|Year of Conference||Publication Type||Title|
|2015||Journal Article||R. Bhakthavatchalu and M. Nirmala Devi, “Deterministic seed selection and pattern reduction in logic BIST”, International Journal of Applied Engineering Research, vol. 10, pp. 7537-7551, 2015.[Abstract]|
|2015||Journal Article||K. Balamurugan, M. Nirmala Devi, and Jayakumar, M., “Performance analysis of 60 GHZ low noise amplifiers using multi-gate mosfets”, Journal of Theoretical and Applied Information Technology, vol. 77, pp. 373-381, 2015.[Abstract]|
|2015||Journal Article||R. Bhakthavatchalu, Kannan, S. K., and M. Nirmala Devi, “Verilog design of programmable JTAG controller for digital VLSI IC's”, Indian Journal of Science and Technology, vol. 8, 2015.[Abstract]|
|2015||Journal Article||R. Bhakthavatchalu and M. Nirmala Devi, “Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture”, International Journal of Engineering and Technology, vol. 7, no. 3, pp. 973-984, 2015.[Abstract]|
|2015||Journal Article||R. Lavanya, Nagarajan, N., and M. Nirmala Devi, “Computer-aided Diagnosis of Breast Cancer by Hybrid Fusion of Ultrasound and Mammogram Features”, Advances in Intelligent Systems and Computing, vol. 325, pp. 403–409, 2015.[Abstract]|
|2015||Journal Article||A. Indoria, Varrun, V., Reddy, M. Krishna, Sathyasai, T., Anand, B., and M. Nirmala Devi, “State Variable Filter Design Using Improvised Particle Swarm Optimization Algorithm”, Advances in Intelligent Computing and Systems (AISC) series, vol. 325, pp. 71–78, 2015.[Abstract]|
|2014||Journal Article||K. Balamurugan, M. Nirmala Devi, and Jayakumar, M., “Design of V-band low noise amplifier using current reuse topologies”, International Journal of Applied Engineering Research, vol. 9, pp. 27319-27330, 2014.[Abstract]|
|2012||Journal Article||P. R. Sruthi and M. Nirmala Devi, “A modified scheme for simultaneous reduction of test data volume and testing power”, Sixteenth International Symposium on VLSI Design and Test (VDAT 2012, vol. 7373 LNCS, pp. 198-208, 2012.[Abstract]|
|2010||Journal Article||M. Nirmala Devi and Arumugam, S., “VLSI implementation of artificial neural networks - A survey”, International Journal of Modelling and Simulation, vol. 30, pp. 148-154, 2010.[Abstract]|
|2009||Journal Article||M. Nirmala Devi, Mohankumar, N., and Arumugam, S., “Modeling and analysis of neuro–genetic hybrid system on FPGA”, Elektronika ir Elektrotechnika (International Journal of Electrical and Electronics Engineering (JEEE)), vol. 96, pp. 69-74, 2009.[Abstract]|
|Year of Conference||Publication Type||Title|
|2014||Conference Paper||R. Bhakthavatchalu, Krishnan, S., Vineeth, V., and M. Nirmala Devi, “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.[Abstract]|
|2014||Conference Paper||B. Anand, Aakash, I., ,, Varrun, V., Reddy, M. K., Sathyasai, T., and M. Nirmala Devi, “Improvisation of particle swarm optimization algorithm”, in 2014 International Conference on Signal Processing and Integrated Networks, SPIN 2014, Noida, 2014, pp. 20-24.[Abstract]|
|2014||Conference Paper||S. Sarathkrishna, Balamurugan, K., M. Nirmala Devi, and Jayakumar, M., “Design and analysis of GaN HEMT based LNA with CPW matching”, in 2014 Eleventh International Conference on Wireless and Optical Communications Networks (WOCN), , 2014.[Abstract]|
|2012||Conference Paper||P. R. Sruthi and M. Nirmala Devi, “Modified AVR Code for Test Data Compression”, in 7th International Workshop on Unique Chips and Systems (UCAS-7) in conjunction with 18th International Symposium on High Performance Computer Architecture, IEEE Computer Society, New Orleans, Louisiana, USA, 2012.|
|2011||Conference Paper||A. Scaria, D. Nath, B., M. Nirmala Devi, and Mohankumar, N., “Hardware implementation of svd based colour image watermarking in wavelet domain”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]|
|Year of Conference||Publication Type||Title|
|2014||Conference Proceedings||B. S. Mahalakshmi, Manikantan, S., Bhavana, P., Prem, A. M., SaiEknaath, R. S. S., and M. Nirmala Devi, “Small signal modelling of GaN HEMT at 70GHz”, International Conference on Signal Processing and Integrated Networks (SPIN), 2014 . IEEE, Noida, Delhi-NCR, India, pp. 739 - 743, 2014.[Abstract]|
|2014||Conference Proceedings||J. Sirisha, C., N. Vaishnavi, P., N. K., S., S. Vidhya, G., Y., Balamurugan, K., M. Nirmala Devi, and M., J., “Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, pp. 1-8, 2014.[Abstract]|
|2014||Conference Proceedings||R. Bhakthavatchalu, M. Nirmala Devi, and Krishnan, S., “Reconfigurable Logic Built in Self-Test technique for SoC Applications”, International Conference on Communication and Computing, ICC 2014, vol. 3. Elsevier, Bangalore, India, pp. 16-23, 2014.|
|2014||Conference Proceedings||P. Sankar and M. Nirmala Devi, “Particle Swarm Optimization with Different Modifications”, Third International Conference on Recent Trends in Engineering and Technology. Elsevier Science and Technology, Chanwad, pp. 551-556, 2014.|
|2014||Conference Proceedings||M. Vijitha and M. Nirmala Devi, “Test data Volume Reduction Using Compressed Scan Mode Architecture”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, 2014.|
|2013||Conference Proceedings||G. Srujana, Radhika, S., Sonu, S., T. Sai, V., Tharun, V., and M. Nirmala Devi, “Improved Particle Swarm Optimisation with Modified Velocity Calculation”, IEEE Workshop on Computational Intelligence: Theories, Applications and Future Directions. Institute of Technology (IIT), Kanpur, pp. 108-113, 2013.|
|2011||Conference Proceedings||Na Haridas and M. Nirmala Devi, “Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST”, ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, vol. 1. Kanyakumari, pp. 350-354, 2011.[Abstract]|
|2011||Conference Proceedings||N. Mohankumar, M. Nirmala Devi, D. Nath, B., and Scaria, A., “VLSI architecture for compressed domain video watermarking”, First International Workshop on Peer-to-Peer Networks and Trust Management, vol. 205 CCIS. Springer in Communications in Computer and Information Science (CCIS) Series, Chennai, India, pp. 405-416, 2011.[Abstract]|
|2008||Conference Proceedings||Va Saichand, M. Nirmala Devi, Arumugam, Sc, and Mohankumar, Nd, “FPGA realization of activation function for artificial neural networks”, IEEE 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, vol. 3. IEEE, Taiwan, pp. 159-164, 2008.[Abstract]|
Reviewer and Program Committee Member
- Reviewer - Springer Journal of the Institution of Engineers (India): Series B
- Reviewer - Inderscience International Journal of Information and Communication Technology
- Reviewer for the International Conference- VLSI- SATA- 2015, 2016.
- Reviewer & PC member- International Symposium- VDAT- 2015
- Reviewer for the International Journal- Advances in Electrical and Electronic Engineering, VSB- Technical University of Ostrava, Czech Republic, 2014.
- Program committee member & Reviewer of "International Conference on Education (EDU 2014)" to be held in Bangalore, INDIA, 2014.
- Reviewer for the Journal of The Institution of Engineers (India): Series B, India in 2014.
- Reviewer for the International Conference on Embedded Systems ICES 2014, July 3- 5, 2014, Dept. of EEE, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, 2014.
- Program committee member & Reviewer of "The Third International conference on Parallel, Distributed Computing and Applications (IPDCA - 2014)" to be held in Chennai,India.
- Member of the editorial board- Chrome Publishing Group, Noida, NCR Delhi, 2014.