Dr. Purushothaman A. completed B.E. in Electrical and Electronics Engineering from MS University, India in 2002. He pursued an M. Tech. in Applied Electronics from Anna University and received his Ph.D. in Information and Communication Technology from Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar in November 2012. 

His research interests include Nyquist ADC and low-power integrated circuits design. Currently, his research mainly focuses on SA and Pipeline algorithms and design of ultra low-power ADC.



Publication Type: Journal Article
Year of Publication Publication Type Title
2015 Journal Article Purushothaman A. and Parikh, C. D., “A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators”, Circuits, systems and Signal processing, Springer, vol. 34, pp. 2749-2764, 2015.[Abstract]

Comparators are the main components in several analog and mixed-signal systems. Design and synthesis of comparator architectures largely remain an analog designer’s art. In this work, we present a systematic methodology for designing comparators using the method of constrained optimization. Constrained optimization is an equation-based optimization method and requires accurate equations. We propose a new delay equation for latch-based comparators. The new delay model is based on Adomian decomposition method and gives more accurate delay characteristics compared with the conventional one. The architecture is optimized for total power dissipation with speed, area and noise as the constraints. Geometric programming-based automation algorithm and the behavioral model of the comparator architecture are written in MATLAB. The optimized schematic is drawn in Cadence 180 nm technology, and the results are verified with MATLAB. © 2015, Springer Science+Business Media New York.

More »»
2015 Journal Article Purushothaman A. and Parikh, C. D., “A low power low area capacitor array based Digital to Analog Converter architecture”, Microelectronics Journal, vol. 46, no. 10, pp. 928–934, 2015.[Abstract]

This paper presents a capacitor based Digital to Analog Converter architecture, which gives comparable performance with the conventional architecture with approximately half the total capacitance. The proposed architecture reduces the area and power dissipation in comparison with the conventional scheme. Further to these advantages, the proposed DAC architecture does not demand an additional reference voltage or an additional switching circuit. Closed form formulas to estimate the standard deviation of INL, DNL and the power consumption are derived. A comparison is also made between the standard architectures and the proposed architecture for the same unit capacitor, in addition to analyzing the capacitor parasitics and mismatches. These analytical comparisons are validated by simulating the proposed architecture and all the other conventional architectures for 10 bits with UMC 180 nm CMOS technology.

More »»
Publication Type: Conference Paper
Year of Publication Publication Type Title
2011 Conference Paper Purushothaman A. and Parikh, C. D., “Automating the design of Successive Approximation Register Analog to Digital Converters”, in 11th International Symposium on VLSI Design and Test, 2011.
2010 Conference Paper Purushothaman A. and Parikh, C. D., “Design of static latch based comparator using power constrained optimization”, in 10th International Symposium on VLSI Design and Test, 2010.
2008 Conference Paper Purushothaman A. and Kumar, C. V. Vijaya, “Implementation of bit level Super systolic RLS adaptive filter using FPGA”, in 10th International Conference on Radio Science (ICRS), 2008.
Faculty Details


Faculty Email: