Karthigha Balamurugan currently serves as Assistant Professor at Department of Electronics and Communication Engineering, School of Engineering, Coimbatore Campus. Her areas of research include Financial Engineering and FPGA Based System Design.


Publication Type: Journal Article
Year of Publication Publication Type Title
2015 Journal Article K. Balamurugan, M. Nirmala Devi, and Jayakumar, M., “Performance analysis of 60 GHZ low noise amplifiers using multi-gate mosfets”, Journal of Theoretical and Applied Information Technology, vol. 77, pp. 373-381, 2015.[Abstract]

Short-channel devices are preferred for realizing millimetre circuits, but these are affected by the short- channel effects (SCE). Multi-Gate (MG) MOSFET is found to be an alternative to overcome this drawback. In this paper, study and analysis of DC and AC parameters of MG MOSFETs have been attempted and small signal gain (y21) of multi-gate structure is analytically derived. Design of low noise amplifier (LNA) at 60 GHz using the channel charging resistance model has been done.Small signal gain and noise figure using the channel charging resistance model has been derived and analysed. The proposed LNA circuit uses various multi-gate MOSFET structures and the results are compared with conventional MOSFET based design. The designed LNA using a Quadruple Gate structure exhibited the noise figure improvement of 24.4% and 42.79% when operated at 1 V and 1.5 V respectively. Also the corresponding gain increases by 2.38 times and 4.9 times compared with conventional single gate MOSFET design. © 2005 - 2015 JATIT & LLS. All rights reserved.

More »»
2014 Journal Article K. Balamurugan, M. Nirmala Devi, and Jayakumar, M., “Design of V-band low noise amplifier using current reuse topologies”, International Journal of Applied Engineering Research, vol. 9, pp. 27319-27330, 2014.[Abstract]

This paper presents the design of single stage, cascode Low Noise Amplifier (LNA) at V-band using current reuse topologies. First, the design of source inductor and gate inductor of cascode transistor are done by considering its small signal equivalents. For this, the output resistance, the internode resistance, the terminal and the gate-source capacitances of cascode amplifier are considered and exploited to determine the value of source and gate inductance. This results in compact and efficient LNA design. Compared to the conventional cascode design, the forward gains at 60 GHz using current reuse source inductor, gate inductor and its combination increases by 8.71%, 52.7% and 64.6% respectively. In second part, the proposed work describes the LNA circuit that uses the design of inductive load thereby achieving reduced VDD supply at common gate transistor. The forward gain and noise figure obtained from this method are 5.8 dB and 2.3 dB respectively. Power consumption of LNA design having inductive load is 7.43 mW that is comparatively lower than the conventional cascode design, which consumes 8.11 mW. For the two designs, IIP3 obtained are -3 dBm and -1 dBm respectively and found to be in good agreement with the expected response. © Research India Publications.

More »»
Publication Type: Conference Paper
Year of Publication Publication Type Title
2014 Conference Paper B. Vinod, Balamurugan, K., and Jayakumar, M., “Design of CMOS based reconfigurable LNA at millimeter wave frequency using active load”, in 2014 IEEE International Conference on Advanced Communication, Control and Computing Technologies, ICACCCT 2014, 2014, pp. 713-718.[Abstract]

Due to increased commercial and scientific applications in millimeter wave (mm wave) band, the development of mm wave transceivers is considered as prominent phase in RFIC design cycle. This paper proposes the design of reconfigurable low noise amplifier (LNA) working at 60 GHz using active load transistor. A single stage source degenerated LNA has been designed to achieve a gain of 8.38 dB and noise figure (NF) of 2.92 dB. The frequency of operation is tuned from 57 to 64 GHz i.e. at millimeter wave. Variation in gain and noise figure are achieved through the design of active load using NMOS transistor. This active load works as reconfiguration network which is subjected to proper bias voltage that yields the highest gain of 8.41 dB and the lower possible gain of 6.9 dB. Similarly the results of NF reaching 2.92 dB as minimum value and on the other end reaching 3.3 dB are observed and presented. That is, reconfigurable performance parameters are gain and NF whose variability is observed to be 17.66 % and 13% respectively. Proper bias voltage is extracted using DC characteristics of load transistor and their results are presented. Design parameter of LNA at millimeter wave frequencies, consideration of noise sources and its equivalent noise voltages, device modeling considering the parasitic effect and choice of LNA configuration have also been discussed. © 2014 IEEE.

More »»
2014 Conference Paper M. Archanaa and Balamurugan, K., “Analysis of thermal noise and noise reduction in CMOS device”, in International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 , 2014.[Abstract]

Advanced CMOS technology assures CMOS device as a good choice for physical realization of RF applications. But as scaling progresses, noise and short channel effect start to deteriorate the device performance, thus increasing the power dissipation. This work focuses on the analysis of thermal noise by varying the gate resistance and frequency. Equivalent noise voltage is calculated for various extracted gate resistance and the effect of distributed gate resistance due to wider channel MOS is analyzed. Thermal noise is reduced using multifinger gate structure when compared to conventional nMOS. A complete small signal equivalent of nMOS along with augmented equivalent noise models is discussed. More »»
Faculty Details


Faculty Email: