Kayalvizhi N. currently serves as Assistant Professor at the department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore Campus. She pursued her BE from Bharathiar University in 2002 and M.Tech. from NIT Calicut in 2008.



Membership in Professional Bodies

  • Member, IETE

Research Expertise

Ongoing PhD Work

  • Non- invasive and non-intrusive blood pressure monitoring

PG and UG projects:

  • Routing Algorithm for VLSI circuits
  • Vedic Multiplier
  • A PPT acquisition setup.
  • Heart rate monitoring using PPG signals.
  • Finding correlation between ABP and PPG Signals
  • Adiabatic Technique for designing Energy Efficient Logic circuits.
  • Reconfigurable multipliers
  • Low power march test pattern generator.
  • Comparision of parallel summation and weak inversion based logarithmic amplifier.


  • Digital circuits and system
  • Electronic circuits
  • Analog integrated circuits
  • Solid State Devices
  • Electric circuits


Publication Type: Journal Article
Year of Publication Publication Type Title
2015 Journal Article P. Paul and Kayalvizhi, N. M. N., “A 4.2ppm/°C temperature compensated CMOS voltage reference”, International Journal of Applied Engineering Research, vol. 10, pp. 23739-23746, 2015.[Abstract]

A voltage reference circuit compatible with latest CMOS standards and temperature stability was developed using 90nm CMOS technology. The circuit includes CMOS transistors operating in saturation and triode regions, without the aid of resistors, diodes and bipolar transistors. In a band gap voltage reference circuit, the temperature independent reference voltage is attained by the base emitter voltages of the bipolar transistors used. In the proposed circuit these bipolar transistors and resistors are replaced by ratioed MOS transistors. The CMOS transistors were biased and designed in such a way that the temperature dependencies of mobility and gate oxide were nullified. The circuit was developed for a constant reference voltage of 1.03V with a temperature coefficient of 4.2ppm/°C, over a range of 0-160 °C. The circuit was operated with a supply voltage of 1.8V and draws a maximum value of supply current as 9.05μA and maximum power dissipation was 77.73μW. © Research India Publications.

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2015 Journal Article N. M. N. Kayalvizhi and Mathew, N., “A 2.89ppm/°C Current Reference Generation with Temperature Compensation using 90-nm CMOS Circuit”, International Journal of Applied Engineering Research , vol. 10, no. 12, pp. 32363-32369, 2015.[Abstract]

This paper presents a low-power and low-voltage CMOS based reference current system, stable against temperature variation using 90 nm CMOS technology. Comparatively less power consumption of 2.02 μW is achieved by the circuit. The circuit is intended to compensate the variation in threshold voltage and mobility of MOSFETs with temperature. MOSFETs in this circuit are biased at their ZTC point to achieve temperature compensation and the circuit generates a reference current that is compensated against temperature variation. It attains a temperature coefficient of 2.89 ppm/°C for a drift of 20°C to 160°C.

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2014 Journal Article N. M. N. Kayalvizhi, “Comparison of Parallel Summation and Weak Inversion Based Logarithmic Amplifier”, International Journal of Research in Engineering and Technology (IJRET), vol. 3, no. 24, pp. 1-5, 2014.[Abstract]

Logarithmic amplifier is used for reducing the dynamic range of the input signal. Logarithmic amplifier is implemented using two different techniques. One of the methods is a parallel summation based method and the other one is a weak inversion based method. In parallel summation based method the transistors are maintained in saturation whereas in weak inversion based method the transistors are maintained in weak inversion. Both methods are simulated in 50nm CMOS technology using HSPICE. Considering power, area and dynamic range weak inversion method is more efficient compared to parallel summation method.

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2012 Journal Article C. S. Shari Jahan and Kayalvizhi, N. M. N., “Adiabatic technique for designing energy efficient logic circuits”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 100-107, 2012.[Abstract]

Energy minimization is an important factor in designing digital circuits which are portable and battery operated.Irreversible logic operation causes the minimum dissipation of KT ln 2 joules of heat energy when each bit is erased.Reversible logic that employs adiabatic switching principles can be used to minimize dynamic power , which is the major contributor to total power dissipation. Reversible Energy Recovery Logic (RERL) belongs to fully adiabatic logic family and it eliminates non adiabatic energy loss by making use of reversible logic. RERL NAND/AND gate and RERL SR latch is proposed in this work using eight phase clocking scheme. This RERL circuits consume less energy compared with static CMOS logic circuits at low speed operation. The simulation result using HSPICE shows that RERL circuits consume less power compared with the static CMOS circuits. © 2012 Springer-Verlag.

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2012 Journal Article N. M. N. Kayalvizhi, “Implementation of Power Efficient Vedic Multiplier”, International Journal of Computer Applications, vol. 43, no. 16, 2012.[Abstract]

Vedic multiplier is based on the ancient algorithms (sutras) followed in INDIA for multiplication. This work is based on one of the sutras called "Nikhilam Sutra". These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes more power than the conventional ones. This paper presents a technique to modify the architecture of the Vedic multiplier by using some existing methods in order to reduce power. The 32 X 32 Vedic multiplier is coded in Verilog HDL and Synthesized using Synopsys Design Compiler. The performance is compared in terms of area, data arrival time and power with earlier existing architecture of Vedic multiplier. The proposed design shows very good improvements in terms of power. More »»
2011 Journal Article S. S. Sakthi and Kayalvizhi, N. M. N., “Power Aware Reconfigurable Multiplier for DSP Applications”, International Journal of Computer Science & Engineering Technology (IJCSET), vol. 1, no. 5, pp. 234-237 , 2011.[Abstract]

DSP applications are rich in multiplication operations. Hence there is a growing need in improving the efficiency of multipliers. To improve the performance of multipliers, reconfiguration is introduced. In this paper, reconfiguration is introduced in the form of one level recursive architecture to the existing modified booth multiplier (MBM). It provides reconfigurable modes that satisfy multiple precision requirements. Power consumption of the multipliers can be reduced with the introduction of power efficient schemes namely Dynamic Operand Interchange and Spurious Power Suppression Technique to the reconfigurable booth architecture. More »»
2010 Journal Article A. Raj and Kayalvizhi, N. M. N., “High throughput multipliers using delay equalization”, International Journal of Computer Applications , vol. 2, 2010.
Publication Type: Conference Paper
Year of Publication Publication Type Title
2011 Conference Paper S. S. Sakthi and Kayalvizhi, N. M. N., “Power aware and high speed reconfigurable modified booth multiplier”, in 2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, Trivandrum, Kerala, 2011, pp. 352-356.[Abstract]

Multiplier is one of the major arithmetic operations carried out in DSP applications. Multiplier architecture is reconfigured so as to enhance their performance and thereby improving the efficiency of the applications. This Reconfigurable multiplier is adapted at run time to satisfy multiple precision requirements of DSP applications. Power consumption of the multipliers is reduced with the introduction of power efficient scheme Dynamic Operand Interchange to the reconfigurable booth architecture. Implementation is done in Verilog and simulated using MODELSIM. Power and Timing analysis is done using Altera Quartus II tool (version 9.0) © 2011 IEEE.

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2009 Conference Paper G. C. V., Kayalvizhi, N. M. N., and M., M., “Generation of New March Tests with Low Test Power and High Fault Coverage by Test Sequence Reordering Using Genetic Algorithm”, in Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on, 2009.


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