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Dr. Nirmala Devi M.

Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: Ph.D
m_nirmala@cb.amrita.edu
Research Interest: Soft Computing, Very-Large-Scale Integration (VLSI) Design of Artifiial Neural Networks

Bio Publications Awards Major Research Objectives PhD Program and Area of Focus Funded Projects
Bio

Dr. M. Nirmala Devi obtained her B.E. degree in Electronics and Communication Engineering (ECE) in 1990 and M. E. (Applied Electronics) Degree in 1996 from Government College of Technology, Coimbatore, Bharathiar University. She is currently working as the Professor in Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. During her tenure at Amrita, she received her Ph. D. degree in the area of VLSI Design of Artificial Neural Networks from Anna University, Chennai in 2010. She has been the coordinator for M. Tech. VLSI Design program.

She has delivered invited lectures on VLSI Design in AICTE and UGC sponsored faculty development programs and conferences. She has also organized a few in-house workshops on “Analog and Digital VLSI Designs and tools”. Moreover she has organized the “National Symposium on Green Electronics” during December 2014. She has served as Board of Studies member for some institutions. She is the recipient of “Appreciation Award” from Amrita Institute of Technology during the year 2003. Moreover, Marquis Who’s Who in the World 2011 distinguishes her as one of the leading achievers from around the country. Furthermore, International Biographical Centre, Cambridge, England has chosen her for inclusion in the prestigious publication “2000 Outstanding Intellectuals of the 21st Century – 2011”. Her areas of interest include VLSI Design and Testing, Computational Intelligence, Hardware Security and Trust, Evolvable Hardware and RF CMOS System Design. She has published around 55 papers in the International Journals and Conferences in her field of expertise. She has served as the reviewer for international conferences and international journals which include the following;

  1. Springer Journal of the Institution of Engineers (India): Series B
  2. Inderscience Int. Journal of Information and Communication Technology
Publications

Journal Article

Year : 2021

Fault detection in satellite power system using convolutional neural network

Cite this Research Publication : Dr. Lavanya R., Devi, N., and Ganesan, M., “Fault detection in satellite power system using convolutional neural network”, Telecommunication Systems, vol. 76, pp. 1-7, 2021.

Publisher : Telecommunication Systems

Year : 2019

Analysis of circuits for security using logic encryption

Cite this Research Publication : B. Chandini and M. Devi, N., “Analysis of circuits for security using logic encryption”, Communications in Computer and Information Science, vol. 969, pp. 520-528, 2019.

Publisher : Communications in Computer and Information Science

Year : 2018

A Selective Generation of Hybrid Random Numbers via Android Smart Phones

Cite this Research Publication : Ashok Kumar Mohan, Dr. Nirmala Devi M., Dr. M. Sethumadhavan, and Santhya R, “A Selective Generation of Hybrid Random Numbers via Android Smart Phones”, International Journal of Pure and Applied Mathematics, vol. 118, no. 8, pp. 311-317, 2018.

Publisher : International Journal of Pure and Applied Mathematics

Year : 2017

Malicious hardware detection and design for trust: An analysis

Cite this Research Publication : S. R. Ranjani and M. Nirmala Devi, “Malicious hardware detection and design for trust: An analysis”, Elektrotehniski Vestnik/Electrotechnical Review, vol. 84, pp. 7-16, 2017.

Publisher : Elektrotehniski Vestnik/Electrotechnical Review, Electrotechnical Society of Slovenia

Year : 2017

Hardware Trojan Detection Using Effective Test Patterns and Selective Segmentation

Cite this Research Publication : A. K. Sashank, Reddy, H. S., Pavithran, P., Akash, M. S., and M. Devi, N., “Hardware Trojan Detection Using Effective Test Patterns and Selective Segmentation”, Communications in Computer and Information Science, vol. 746, pp. 379-386, 2017.

Publisher : Communications in Computer and Information Science

Year : 2017

Golden-chip free power metric based hardware trojan detection and diagnosis

Cite this Research Publication : R. S. Ranjani and Dr. Nirmala Devi M., “Golden-chip free power metric based hardware trojan detection and diagnosis”, Far East Journal of Electronics and Communications, vol. 17, pp. 517-530, 2017.

Publisher : Far East Journal of Electronics and Communications, Pushpa Publishing House,

Year : 2015

State Variable Filter Design Using Improvised Particle Swarm Optimization Algorithm

Cite this Research Publication : A. Indoria, Varrun, V., Reddy, M. Krishna, Sathyasai, T., Anand, B., and Dr. Nirmala Devi M., “State Variable Filter Design Using Improvised Particle Swarm Optimization Algorithm”, Advances in Intelligent Computing and Systems (AISC) series, vol. 325, pp. 71–78, 2015.

Publisher : Springer

Year : 2015

Verilog design of programmable JTAG controller for digital VLSI IC’s

Cite this Research Publication : Dr. Ramesh Bhakthavatchalu, Kannan, S. K., and Dr. Nirmala Devi M., “Verilog design of programmable JTAG controller for digital VLSI IC's”, Indian Journal of Science and Technology, vol. 8, 2015.

Publisher : Indian Society for Education and Environment

Year : 2015

Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture

Cite this Research Publication : Dr. Ramesh Bhakthavatchalu and Dr. Nirmala Devi M., “Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture”, International Journal of Engineering and Technology, vol. 7, no. 3, pp. 973-984, 2015.

Publisher : International Journal of Engineering and Technology

Year : 2015

Deterministic seed selection and pattern reduction in logic BIST

Cite this Research Publication : Dr. Ramesh Bhakthavatchalu and Dr. Nirmala Devi M., “Deterministic seed selection and pattern reduction in logic BIST”, International Journal of Applied Engineering Research, vol. 10, pp. 7537-7551, 2015.

Publisher : Research India Publications

Year : 2012

A modified scheme for simultaneous reduction of test data volume and testing power

Cite this Research Publication : P. R. Sruthi and Dr. Nirmala Devi M., “A modified scheme for simultaneous reduction of test data volume and testing power”, Sixteenth International Symposium on VLSI Design and Test (VDAT 2012, vol. 7373 LNCS, pp. 198-208, 2012.

Publisher : Springer - Lecture Notes in Computer Science

Year : 2010

VLSI implementation of artificial neural networks – A survey

Cite this Research Publication : Dr. Nirmala Devi M. and Arumugam, S., “VLSI implementation of artificial neural networks - A survey”, International Journal of Modelling and Simulation, vol. 30, pp. 148-154, 2010.

Publisher : Taylor & Francis

Conference Paper

Year : 2017

LFSR Based Secured Scan design Testability Techniques

Cite this Research Publication : M. I. Shiny and M. Devi, N., “LFSR Based Secured Scan design Testability Techniques”, in Procedia Computer Science, 2017, vol. 115, pp. 174-181.

Publisher : Procedia Computer Science

Year : 2014

Deterministic seed selection and pattern reduction in logic BIST

Cite this Research Publication : Dr. Ramesh Bhakthavatchalu, Krishnan, S., Vineeth, V., and Dr. Nirmala Devi M., “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.

Publisher : IEEE Computer Society

Year : 2014

Design and Analysis of GaN HEMT based LNA with CPW matching

Cite this Research Publication : S. Sarathkrishna, Karthigha Balamurugan, Dr. Nirmala Devi M., and Dr. Jayakumar M., “Design and Analysis of GaN HEMT based LNA with CPW matching”, in 2014 Eleventh International Conference on Wireless and Optical Communications Networks (WOCN), , 2014.

Publisher : IEEE

Year : 2014

Improvisation of particle swarm optimization algorithm

Cite this Research Publication : B. Anand, Aakash, I., ,, Varrun, V., Reddy, M. K., Sathyasai, T., and Dr. Nirmala Devi M., “Improvisation of particle swarm optimization algorithm”, in 2014 International Conference on Signal Processing and Integrated Networks, SPIN 2014, Noida, 2014, pp. 20-24.

Publisher : IEEE Computer Society

Year : 2012

Modified AVR Code for Test Data Compression

Cite this Research Publication : 7th International Workshop on Unique Chips and Systems (UCAS-7) in conjunction with 18th International Symposium on High Performance Computer Architecture, IEEE Computer Society, New Orleans, Louisiana, USA (2012)

Publisher : IEEE Computer Society

Year : 2011

Hardware implementation of svd based colour image watermarking in wavelet domain

Cite this Research Publication : A. Scaria, D. Nath, B., Dr. Nirmala Devi M., and N Mohankumar, “Hardware implementation of svd based colour image watermarking in wavelet domain”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.

Publisher : PACC 2011

Conference Proceedings

Year : 2014

Small signal modelling of GaN HEMT at 70GHz

Cite this Research Publication : B. S. Mahalakshmi, Manikantan, S., Bhavana, P., Prem, A. M., SaiEknaath, R. S. S., and Dr. Nirmala Devi M., “Small signal modelling of GaN HEMT at 70GHz”, International Conference on Signal Processing and Integrated Networks (SPIN), 2014 . IEEE, Noida, Delhi-NCR, India, pp. 739 - 743, 2014.

Publisher : IEEE

Year : 2014

Particle Swarm Optimization with Different Modifications

Cite this Research Publication : P. Sankar and Dr. Nirmala Devi M., “Particle Swarm Optimization with Different Modifications”, Third International Conference on Recent Trends in Engineering and Technology. Elsevier Science and Technology, Chanwad, pp. 551-556, 2014.

Publisher : Elsevier Science and Technology

Year : 2014

Reconfigurable Logic Built in Self-Test technique for SoC Applications

Cite this Research Publication : Dr. Ramesh Bhakthavatchalu, Dr. Nirmala Devi M., and Krishnan, S., “Reconfigurable Logic Built in Self-Test technique for SoC Applications”, International Conference on Communication and Computing, ICC 2014, vol. 3. Elsevier, Bangalore, India, pp. 16-23, 2014.

Publisher : Elsevier

Year : 2014

Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models

Cite this Research Publication : J. Sirisha, C., N. Vaishnavi, P., N. K., S., S. Vidhya, G., Y., Karthigha Balamurugan, Dr. Nirmala Devi M., and M., J., “Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, pp. 1-8, 2014.

Publisher : Elsevier

Year : 2014

Test data Volume Reduction Using Compressed Scan Mode Architecture

Cite this Research Publication : M. Vijitha and Dr. Nirmala Devi M., “Test data Volume Reduction Using Compressed Scan Mode Architecture”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, 2014.

Publisher : Elsevier

Year : 2013

Improved Particle Swarm Optimisation with Modified Velocity Calculation

Cite this Research Publication : G. Srujana, Radhika, S., Sonu, S., T. Sai, V., Tharun, V., and Dr. Nirmala Devi M., “Improved Particle Swarm Optimisation with Modified Velocity Calculation”, IEEE Workshop on Computational Intelligence: Theories, Applications and Future Directions. Institute of Technology (IIT), Kanpur, pp. 108-113, 2013.

Publisher : IEEE Workshop on Computational Intelligence: Theories, Applications and Future Directions

Year : 2011

Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST

Cite this Research Publication : Na Haridas and Dr. Nirmala Devi M., “Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST”, ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, vol. 1. Kanyakumari, pp. 350-354, 2011.

Publisher : ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology

Year : 2008

FPGA Realization of Activation Function for Artificial Neural Networks

Cite this Research Publication : Va Saichand, Dr. Nirmala Devi M., Arumugam, Sc, and N Mohankumar, “FPGA Realization of Activation Function for Artificial Neural Networks”, IEEE 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, vol. 3. IEEE, Taiwan, pp. 159-164, 2008.

Publisher : IEEE

Awards
  • Appreciation Award – Amrita Institute of Technology & Science- 2003
  • Marquis Who’s Who in the World- 2011
  • 2000 Outstanding Intellectuals of the 21st Century- 2011 – International Biographical Center, Cambridge, England.
Major Research Objectives
  • VLSI Design & Testing– Development of efficient algorithms for VLSI testing and extending it to focus on low power concept with compression schemes
  • RF CMOS System design– Application of CMOS or GaN technology in the design of RF transceiver systems at L, S, and C bands
  • Hardware Security & Trust– Enhancing the security of VLSI chips in safety critical applications like missiles & biomedical implants
  • Computational Intelligence– Application the high potential intelligence concepts like Neural networks, Particle Swarm Optimization, Genetic Algorithms etc., on social and health related problems like perception engineering & cancer Diagnosis for the improvement
  • Evolvable Hardware– Emulation of efficient and optimized algorithms on FPGAs to develop proof-of-concept.
PhD Program and Area of Focus
  1. Secured testing of VLSI Circuits
  2. VLSI Testing and Security
  3. Design for Security
  4. Antenna Design & Optimization
  5. Hardware Design for Trust
  6. Security in Multi-core Architectures
  7. RF CMOS Design of Low-noise Amplifier
Funded Projects

Title of the Research proposal– Hardware Trojan Detection and Consistency based Diagnosis

Investigators– Dr. Nirmala Devi M., Dr. Jayakumar M., Mohankumar N., Dr. Sethumadhavan M.

Funding Agency– DRDO, New Delhi

Period– Two Years

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