Dr. Madhav Datta is the Chairman of ACIRI and a Distinguished Professor in the department of Chemical Engineering and Materials Science. He has over 40 years of industrial and academic research experience having worked at IBM’s T.J. Watson Research Center, Intel’s Logic Technology Development, Emerson Network Power’s (ENP) Cooligy Precision Cooling, and the Materials Department of Ecole Polytechnique Federale de Lausanne (EPFL). His research interests include: Electronic Materials and Processing, Micro Cooling Devices, Wafer-Level Packaging, Joining Technologies, Electrochemical Processing, and Materials Characterization. Dr. Datta is an innovator with 48 issued US Patents.and is recipient of the Electrodeposition Research Award of the Electrochemical Society. Dr. Datta received his doctorate from the Materials Department of Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland.

He was awarded with Ninth Plateau of IBM Invention Achievement Awards and IBM’s Top 5% Patent award. He has authored 90+ publications and is the author/editor of several books on Electrochemical Processing & Micro/Nano electronics. He is recipient of the Electrodeposition Research Award of the Electrochemical Society. International Biographical Center, Cambridge, England included his name in outstanding scientists of the 20th Century in honor of his outstanding contribution in the field of Electrochemical Microfabrication. He has held several administrative positions including divisional chairs in the Electrochemical Society and the International Society of Electrochemistry. He has organized several international symposia and has presented keynote and invited lectures.. 

Dr. Datta received his BS in Chemical Engineering from H.B. Technological Institute, Kanpur, MS from University of California at Los Angeles.

Education

YEAR DEGREE/PROGRAM INSTITUTION
1975 D.Sc. Tech. Materials Department, Swiss Federal Institute of Technology (Ecole Polytechnique Fédérale de Lausanne, EPFL), Lausanne, Switzerland
1970 M. S. in Chemical Engineering School of Engineering and Applied Sciences, University of California, Los Angeles
1968 B. S. in Chemical Engineering H. B. Technological Institute, Kanpur, India

Experience

YEAR AFFILIATION
September 2014 – Present Distinguished Professor, Chemical Engineering & Materials Science, Amrita Vishwa Vidyapeetham
October 2008 – September 2014 Adjunct Professor, Department of Chemical Engineering and Materials Science, Amrita Vishwa Vidyapeetham
November 2003-April 2013 Chief Scientist/Chief Engineer, Cooligy Precision Cooling, Emerson Network Power, 800 Maude Avenue, Mountain View, CA 94034
August 1999 – October 2003 Senior Manager/ Group Leader, Intel Corporation, Logic Technology Development, Hillsboro, OR 97124
November 1984-July 1999 Manager/Research Staff Member, IBM Corporation, T.J. Watson Research Center, Yorktown Heights, NY 10598
October 1984 – September 1985 Assistant Research Manager , R & D Center for Iron and Steel, Steel Authority of India Ltd., Ranchi - 834002, India
September 1975- September 1984   Senior Scientist/Teaching Staff,  Swiss Federal Institute of Technology, Lausanne, Switzerland

Areas of Research Interest

  1. Electronic Materials: Micro/Nano Fabricated Tailored Materials and Structures for Microelectronic packaging; Flip-chip (C4) technology; Lead-free Packaging Materials.
  2. Materials Processing: Electrodeposition, Etching, Electropolishing, Anodization; Advanced Joining Processes for metal-metal, metal-ceramic bonding.
  3. Energy Technologies: Li-metal and Li-ion battery technologies for Electronics; Solar cells.
  4. Thermal Management: Energy Efficient Liquid Cooling Systems for Electronic and Photonic Devices; Micro-Heat Exchanger and Micro-Fluidics devices.
     

Research

Projects (Ongoing)

Durability of High Performance Nano Adhesive Bonding of Aluminium under Aerospace Environments
 

Projects (Submitted)

Publications

Publication Type: Journal Article
Year of Publication Publication Type Title
2015 Journal Article M. Datta and Choi, H. - W., “Microheat exchanger for cooling high power laser diodes”, Applied Thermal Engineering, vol. 90, pp. 266–273, 2015.[Abstract]

A tremendous amount of heat is generated during operation of high power laser diodes that are built as a linear array of laser emitters. The present paper describes fabrication and test results of a microheat exchanger for cooling such high power laser diodes. The cooling module consists of two key components: a ceramic-copper bonded thermal conduction plate with twelve conducting pads to which the laser diodes are mounted and a liquid cooled microheat exchanger containing an internal active microstructure. The thermal conduction plate is joined to the microheat exchanger and the heat generated in the laser bar conduction plate is extracted by flowing a cooling liquid through the microheat exchanger. Design and fabrication of different components of the cooling module and their assembly processes are described in this paper. Thermal test results indicate that the cooling system provides uniform liquid flow and heat transfer rate over a large surface, while maintaining low pressure drop at high flow rates. Long term reliability test data demonstrate the robustness of materials, internal microstructure and fabrication processes employed in the present study.

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2015 Journal Article M. Datta, “Microfabrication by High Rate Anodic Dissolution: Fundamentals and Applications”, Electrochemical Society Transactions, vol. 66, no. 22, pp. 1-18, 2015.[Abstract]

This paper presents a review of the basic principles of electrochemical metal removal processes and their application in microfabrication. After a brief description of anodic behavior of metals, the influence of mass transport, surface films and current distribution on microfabrication performance are discussed. Some examples of microelectronic component fabrication are presented that demonstrate the challenges and opportunities offered by high rate anodic dissolution processes.

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2015 Journal Article M. Datta, “Bonded Ceramic-Metal Layers for fabrication of Thermal Conduction Plates”, Journal of Microelectronics and Electronic Packaging, vol. 12, no. 3, pp. 146-152, 2015.[Abstract]

The work described in this article is part of an effort to build reliable and efficient liquid cooling modules for high-power laser diodes. The cooling system is designed to mount at least 12 laser diodes to a common microheat exchanger, thus requiring a large-size thermal conduction plate. Fabrication of the thermal conduction plate involved void-free bonding of copper layers on both sides of an aluminum nitride (AlN) plate. In the current study, ceramic-metal bonding methods using moly-manganese metallization and active metal brazing were investigated. Bonded AlN/copper plates were characterized and evaluated by optical microscopy, scanning electron microscopy, and energy dispersive spectrometry. For detecting voids, cracks, and delamination, some of the plates were analyzed by scanning acoustic microscopy (C-SAM). Results indicated that >99% void-free bonded AlN/Cu plates can be fabricated by using properly selected metallization conditions and brazing temperature profiles. The active metal brazing approach was found to be a cost-effective method of fabricating reliable, void-free thermal conduction plates.

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2009 Journal Article M. Datta, “Paradigm Shifts in Electronics Enabled by Electrochemical Micro/Nano Processing”, Micro and Nanosystems, vol. 1, pp. 83–104, 2009.[Abstract]

Advances in electronic materials, processing technologies, and integration schemes have resulted in phenomenal miniaturization of electronic components. Since the development of through-mask plating for thin film heads in the1960s and 1970s, an enormous amount of industrial and academic R&D effort has positioned electrochemical processing among the most sophisticated processing technologies employed in the microelectronics industry today. Electrochemical processing has thus become an integral part of advanced wafer processing and an enabling technology for nanofabrication. In this review we begin with a brief discussion of the phenomenal advances in IC based electronics and Moore's law as indicators of the paradigm shifts in microelectronics. We then highlight the important role played by electrochemical processing in the electronics industry. A detailed discussion of the dual Damascene plating technology and electroplated C4 technology form the key elements of the review. Finally, the challenges and opportunities offered by these technologies in extending Moore's law are discussed.

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2007 Journal Article M. Datta, Lin, E., Choi, H. - W., McMaster, M., Brewer, R., Werner, D., Hom, J., Upadhya, G., Gopalakrishnan, S., and Rebarber, F., “Liquid Cooling System for Advanced Microelectronics”, ECS Transactions, vol. 6, pp. 13–31, 2007.[Abstract]

Heat removal from advanced microelectronic devices is becoming a major packaging challenge. Thermal management solutions such as microchannel liquid cooling are now becoming commercially available. The use of a liquid cooling system is attractive because of higher heat transfer coefficients or lower thermal resistance as compared to traditional heat pipe or heat sink solutions. In this paper we present a description of the key features of Cooligy's closed loop Liquid Cooling System (LCS). Two key components of the LCS, namely a microheat exchanger and an electrokinetic pump are discussed in detail. Published literature on advanced thermal interface materials and nanofluids are briefly reviewed. Wherever applicable, the importance and impact of electrochemical processing and materials aspects are highlighted.

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2003 Journal Article M. Datta, “Electrochemical processing technologies in chip fabrication: challenges and opportunities”, Electrochimica acta, vol. 48, pp. 2975–2985, 2003.[Abstract]

Cost-performance advantage of electrochemical processing technologies has enabled a paradigm shift in chip making. The dual Damascene process for Cu chip metallization and the C4 (flip-chip) technology for area array chip-package interconnection have placed electrochemical technologies among the most sophisticated fab processing technologies. These processing technologies have now been integrated into 300 mm wafer processing facilities for chip fabrication. New materials and processes are continuously being developed to meet the microprocessor industry's increasing performance and miniaturization trends. Electromigration issues, and the need for novel polishing approaches to integrate ultra low-k dielectric materials with Cu metallization are some of the immediate concerns in chip making. Development of a compliant, cost-effective Pb-free C4 chip-package interconnection is another key objective of the microelectronics industry, which is making an effort to market Pb-free products in few years. All of these developments provide ample opportunities for electrochemical processing technologies.

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2002 Journal Article M. Datta, “Micromachining by electrochemical dissolution”, Micromachining of Engineering Materials, McGeough, J.A., editor, Marcel Dekker Inc., , p. 239, 2002.
2000 Journal Article M. Datta and Landolt, D., “Fundamental aspects and applications of electrochemical microfabrication”, Electrochimica acta, vol. 45, pp. 2535–2558, 2000.[Abstract]

The theory and applications of electrochemical microfabrication technology are reviewed focusing on electrodeposition and dissolution processes. Electrochemical microfabrication offers some unique advantages over competing vapor phase technologies and therefore finds increasing use in the electronics and microsystems industries. The present paper discusses the underlying principles of electrochemical microfabrication processes. The important role of mass transport and current distribution is stressed and it is shown how numerical modeling contributes to the present understanding of critical process parameters. The application of electrochemical microfabrication technology in the electronics industry is illustrated with selected examples.

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2000 Journal Article M. Datta, Atluri, V., Lee, K., Stevenson, K., Tadayon, P., Jones, M., and Berry, M., “Integration of Pb-free Flip-Chip Bumping Process”, Intel Assembly and Test Technology Journal, pp. 247-258, 2000.
Publication Type: Patent
Year of Publication Publication Type Title
2015 Patent M. Datta, Emory, D., Joshi, S. M., Menezes, S., and Suh, D., “Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same”, U.S. Patent US 12/655,9752015.[Abstract]

The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

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2012 Patent M. Datta, Leong, B., and McMaster, M., “Microheat exchanger for laser diode cooling”, U.S. Patent US 12/536,3612012.[Abstract]

A microheat exchanging assembly is configured to cool one or more heat generating devices, such as integrated circuits or laser diodes. The microheat exchanging assembly includes a first ceramic assembly thermally coupled to a first surface, and in cases, a second ceramic assembly thermally coupled to a second surface. The ceramic assembly includes one or more electrically and thermally conductive pads to be thermally coupled to a heat generating device, each conductive pad is electrically isolated from each other. The ceramic assembly includes a ceramic layer to provide this electrical isolation. A top surface and a bottom surface of the ceramic layer are each bonded to a conductive layer, such as copper, using an intermediate joining material. A brazing process is performed to bond the ceramic layer to the conductive layer via a joining layer. The joining layer is a composite of the joining material, the ceramic layer, and the conductive layer.

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2012 Patent M. Datta and McMaster, M., “Bonded metal and ceramic plates for thermal management of optical and electronic devices”, U.S. Patent US 12/536,4022012.[Abstract]

A ceramic assembly includes one or more electrically and thermally conductive pads to be thermally coupled to a heat generating device, each conductive pad is electrically isolated from each other. The ceramic assembly includes a ceramic layer to provide this electrical isolation. The ceramic layer has high thermal conductivity and high electrical resistivity. A top surface and a bottom surface of the ceramic layer are each bonded to a conductive layer, such as copper, using an intermediate joining material. A brazing process is performed to bond the ceramic layer to the conductive layer via a joining layer. The joining layer is a composite of the joining material, the ceramic layer, and the conductive layer. The top conductive layer and the joining layer are etched to form the electrically isolated conductive pads. The conductive layers are bonded to the ceramic layer using a bare ceramic approach or a metallized ceramic approach.

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2010 Patent M. Datta, McMaster, M., Brewer, R., Zhou, P., Tsao, P., Upadhaya, G., and Munch, M., “Method of fabricating high surface to volume ratio structures and their integration in microheat exchangers for liquid cooling system”, U.S. Patent US 11/326,6902010.[Abstract]

An structure and method of manufacturing a microstructure for use in a heat exchanger is disclosed. The heat exchanger comprises a manifold layer and an microstructured region. The manifold layer comprises a structure to deliver fluid to the microstructured region. The microstructured region is formed from multiple windowed layers formed from heat conductive layers through which a plurality of microscaled apertures have been formed by a wet etching process. The plurality of windowed layers are then coupled together to form a composite microstructure.

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2009 Patent M. Datta, Zhou, P., Choi, H. - W., Leong, B., McMaster, M., and Werner, D. E., “Fabrication of high surface area, high aspect ratio mini-channels and their application in liquid cooling systems”, U.S. Patent US 12/571,2652009.[Abstract]

The present invention provides methods and apparatuses which achieve high heat transfer in a fluid cooling system, and which do so with a small pressure drop across the system. The present invention teaches the use of wall features on the fins of a heat exchanger to cool fluid in a fluid cooling system. The present invention also discloses high aspect ratio, high surface area structures applicable in micro-heat exchangers for fluid cooling systems and cost effective methods for manufacturing the same.

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2007 Patent M. Datta, Emory, D., Suh, D., Joshi, S. M., and Menezes, S., “Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same”, U.S. Patent US 10/776,4482007.[Abstract]

The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

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2007 Patent B. Conway, Brewer, R., Tsao, P., Hom, J., Werner, D., Zhou, P., Upadhya, G., Datta, M., Firouzi, A., and Landry, F., “Methodology for the liquid cooling of heat generating components mounted on a daughter card/expansion card in a personal computer through the use of a remote drive bay heat exchanger with a flexible fluid interconnect”, U.S. Patent US 11/800,3032007.[Abstract]

A cooling system includes a cooling unit configured to fit within a single drive bay of a personal computer. The cooling unit includes a fluid-to-air heat exchanger, an air mover, a pump, fluid lines, and control circuitry. The cooling system also includes a cooling loop configured to be coupled to one or more heat generating devices. The cooling loop includes the pump and the fluid-to-air heat exchanger from the cooling unit, and at least one heat exchanger coupled together via flexible fluid lines. The heat exchanger is thermally coupled to the heat generating device. The cooling unit is configured to maintain noise below a specified acoustical specification. To meet this acoustical specification, the size, position, and type of the components within the cooling unit are specifically configured.

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2006 Patent M. Datta, Zhou, P., Hom, J., Munch, M., and McMaster, M., “Re-workable metallic TIM for efficient heat exchange”, U.S. Patent US 11/345,5562006.[Abstract]

A heat exchanging system uses a metallic TIM for efficient heat transfer between a heat source and a heat exchanger. The heat source is preferably an integrated circuit coupled to a circuit board. The metallic TIM preferably comprises indium. The metallic TIM is comprised of either a separate metallic TIM foil or as a deposited layer of metal material. The metallic TIM foil is mechanically joined to a first surface of the heat exchanger and to a first surface of the integrated circuit by applying sufficient pressure during clamping. Disassembly is accomplished by un-clamping the heat exchanger, the metallic TIM foil, and the integrated circuit from each other. Once disassembled, the heat exchanger and the metallic TIM foil are available to be used again. If the metallic TIM is deposited onto the heat exchanger, disassembly yields a heat exchanging sub-assembly that is also reusable.

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2005 Patent M. Datta, Emory, D., Joshi, S. M., Menezes, S., and Suh, D., “Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same”, U.S. Patent US 09/961,0342005.[Abstract]

The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

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2005 Patent P. K. Moon, Ma, Z., and Datta, M., “Under bump metallurgy for Lead-Tin bump over Cu pad”, U.S. Patent US 10/608,4072005.[Abstract]

The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium.
The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.

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2005 Patent M. Datta, “Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps”, U.S. Patent US 10/868,1502005.[Abstract]

A ball-limiting metallurgy stack is disclosed for an electrical device that contains at least one copper layer disposed upon a titanium adhesion metal layer. The ball-limiting metallurgy stack resists tin migration toward the upper metallization of the device. An etch process flow is also disclosed which resists the redepostion of the tin during etching of a copper layer.

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2005 Patent V. M. Dubin, Thomas, C. D., McGregor, P., and Datta, M., “Method of electroless introduction of interconnect structures”, U.S. Patent US 09/753,2562005.[Abstract]

A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point, and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material.

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2004 Patent V. M. Dubin, Thomas, C. D., McGregor, P., and Datta, M., “Interconnect structures and a method of electroless introduction of interconnect structures”, U.S. Patent US 10/290,7762004.[Abstract]

An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a different conductive shunt material.

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2004 Patent P. K. Moon, Ma, Z., and Datta, M., “Under bump metallurgy for lead-tin bump over copper pad”, U.S. Patent US 10/262,2812004.[Abstract]

The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium.
The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.

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2004 Patent M. Datta, Emory, D., Huang, T. -luh, Joshi, S. M., King, C. A., Ma, Z., Marieb, T., Mckeag, M., Suh, D., Yang, S., and , “Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same”, U.S. Patent US 09/961,0372004.[Abstract]

The invention relates to a ball limiting metallurgy stack for an electrical device that contains a tin diffusion barrier and thermo-mechanical buffer layer disposed upon a refractory metal first layer. The multi-diffusion barrier layer stack resists tin migration toward the upper metallization of the device.

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2004 Patent M. Datta, “Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps”, U.S. Patent US 10/279,4782004.[Abstract]

A ball-limiting metallurgy stack is disclosed for an electrical device that contains at least one copper layer disposed upon a titanium adhesion metal layer. The ball-limiting metallurgy stack resists tin migration toward the upper metallization of the device. An etch process flow is also disclosed which resists the redepostion of the tin during etching of a copper layer.

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2003 Patent M. Datta, Gruber, P. A., Rubino, J. M., Sambucetti, C. J., and Walker, G. F., “Method for testing chips on flat solder bumps”, U.S. Patent US 09/301,8892003.[Abstract]

A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

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2001 Patent P. C. Andricacos, Datta, M., Horkans, W. J., Kang, S. K., Kwietniak, K. T., Mathad, G. S., Purushothaman, S., Shi, L., Tong, H. M., and Deligianni, H., “Flip-chip interconnections using lead-free solders”, U.S. Patent US 08/614,9842001.[Abstract]

An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

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2001 Patent M. Datta, Galasco, R. T., Lehman, L. P., Magnuson, R. H., Susko, R. A., and Topa, R. D., “Removal of metal skin from a copper-Invar-copper laminate”, U.S. Patent US 09/347,5812001.[Abstract]

A method of removing a metal skin from a through-hole surface of a copper-Invar-copper (CIC) laminate without causing differential etchback of the laminate. The metal skin includes debris deposited on the through-hole surface as the through hole is being formed by laser or mechanical drilling of a substrate that includes the laminate as an inner plane. Removing the metal skin combines electrochemical polishing (ECP) with ultrasonics. ECP dissolves the metal skin in an acid solution, while ultrasonics agitates and circulates the acid solution to sweep the metal skin out of the through hole. ECP is activated when a pulse power supply is turned on and generates a periodic voltage pulse from a pulse power supply whose positive terminal is coupled to the laminate and whose negative terminal is coupled to a conductive cathode. After the metal skin is removed, the laminate is differentially etched such that the copper is etched at a faster rate than the Invar. To prevent the differential etching, a copper layer is formed on a surface of the substrate with an electrical resistance R1 between the copper layer and the positive terminal of the pulse power supply. Additionally, an electrical resistance R2 is formed between the laminate and the positive terminal of the pulse power supply. Adjustment of R1 and R2 controls the relative etch rates of the copper and the Invar.

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2001 Patent E. Israel Cooper, Datta, M., Jr, T. Edward Din, Kanarsky, T. Safron, Pike, M. Barry, and Shenoy, R. Vaman, “Methods for monitoring components in the TiW etching bath used in the fabrication of C4s”, U.S. Patent US 09/138,4422001.[Abstract]

Monitoring techniques have been developed for direct/indirect determination of metal etching bath components and for managing their replenishment. The disclosed methods have been successfully employed to make TiW etching a robust process that provides minimized and controlled undercutting of ball limited metallurgy and mechanical reliable C4s. A metal etching solution is monitored and replenished by measuring the sulfate concentration of a hydrogen peroxide, soluble salt, and soluble EDTA salt etchant. Turbidimetric titration conditions are used to measure and compare opaqueness of liquids by viewing light through them and determining how much light is cut off. Additional sulfate is added to maintain the sulfate concentration. Water and/or fresh etchant is added to compensate for evaporation or drag.

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2001 Patent J. Michael Cotte, Datta, M., and Kang, S. Kwon, “Reflow of low melt solder tip C4's”, U.S. Patent US 09/359,0612001.[Abstract]

An array of C4 solder bumps and a method for making is described incorporating an array of conductive areas on an electrical device, each conductive area having a layer of ball limited metalurgy at the device surface and two layers of solder having respective melting temperatures to form the C4 structure. The method includes melting the second layer of solder in the down position or towards earth to form a C4 solder ball or bump. The invention overcomes the problem of low temperature solder from wicking over the sidewall surfaces of the high melt solder of the C4 structure and attacking the edges of the underlying seed layers of the ball limited metalurgy.

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2000 Patent J. M. Cotte and Datta, M., “High performance lithium polymer electrolyte battery”, U.S. Patent US 08/915,1342000.[Abstract]

A primary lithium battery particularly adapted for use in self-contained self-powered devices (SSPD) for mobile communication and computing products, such as radio frequency identification tags, PCMCIA cards, and smart cards. The battery utilizes a solid polymer electrolyte membrane that preferably has a polyacrylonitrile matrix. Performance of the electrolyte membrane is optimized by controlling the amount of aprotic organic solvents within the membrane within a prescribed range of ratios. The battery cathode is encapsulated within a polymeric matrix that eliminates the exposure hazard posed by lithium intercalation compounds used within the cathode. Use of stainless steel foil current collectors gives a high open circuit voltage of 3.8 volts and high cell capacity. A method of determining the optimum cathode thickness in the battery is also described. This provides a means of maximizing volumetric and gravimetric energy densities by using the optimum amount of cathode material. Batteries fabricated by using optimal materials can be operated under pulsed and dc discharge conditions over a temperature range between about -40 and +80° C.

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2000 Patent M. Datta, Edelstein, D. Charles, and Uzoh, C. Emeka, “Apparatus and method for the electrochemical etching of a wafer”, U.S. Patent US 08/968,1902000.[Abstract]

An electrochemical etching apparatus and method increasing the rate at which material is removed from a substrate such as a metallic surface. The apparatus includes an electrolyte delivery system positioned below and centered beneath the center of the substrate (e.g., a wafer) to be etched so that the center axis of the delivery system corresponds to the center of the wafer. The electrolyte delivery system and the wafer are then rotated relative to each other as the electrolyte is discharged from the delivery system and toward the surface of the wafer. A corresponding method for electrochemically etching a surface of the wafer with an electrolyte is also provided.

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1999 Patent P. Constantin Andricacos, Datta, M., Horkans, W. Jean, Kang, S. Kwon, and Kwietniak, K. Thomas, “Barrier layers for electroplated SnPb eutectic solder joints”, U.S. Patent US 09/057,2051999.[Abstract]

The present invention provides a means of fabricating a reliable C4 flip-chip structure for low-temperature joining. The electrochemically fabricated C4 interconnection has a barrier layer between the electroplated tin-rich solder bump and the ball-limiting metallurgy that protects the terminal metal in the ball-limiting metallurgy from attack by the Sn in the solder. The barrier layer is electroplated through the same photoresist mask as the solder and thus does not require a separate patterning step. A thin layer of electroplated nickel serves as a reliable barrier layer between a copper-based ball-limiting metallurgy and a tin-lead (Sn--Pb) eutectic C4 ball.

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1999 Patent W. E. Corbin Jr, Datta, M., Dinan, T. E., and Kern, F. W., “Electrochemical etching apparatus and method for spirally etching a workpiece”, U.S. Patent US 08/885,6081999.[Abstract]

Disclosed is an electrochemical etching apparatus including a fixture for holding a workpiece; a nozzle, positioned opposite the fixture and facing the workpiece, for impinging an etchant onto the workpiece; and an electrode for applying a voltage between the electrode and the workpiece; wherein, in operation, one of the fixture and nozzle are rotated and the nozzle is moved radially outwardly so that the workpiece is spirally etched. Also disclosed is a method of spirally etching a workpiece.

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1999 Patent J. M. Cotte, Datta, M., and Shenoy, R., “Lithium polymer electrolyte battery for sub-ambient temperature applications”, U.S. Patent US 08/879,4361999.[Abstract]

A primary lithium battery particularly adapted for use in self-contained self-powered devices (SSPD) for mobile communication and computing products, such as radio frequency identification tags, PCMCIA cards, and smart cards. The battery has a flexible and compact design, and utilizes a solid polymer electrolyte membrane that preferably has a polyacrylonitrile matrix. Performance of the electrolyte membrane is optimized by controlling the amount of aprotic organic solvents within the membrane within a prescribed range of ratios. In so doing, the performance characteristics of the battery closely approximate that of conventional liquid electrolytes without the safety hazards associated with the risk of liquid electrolyte leakage, and exhibit enhanced performance at sub-ambient temperatures. A further feature is that the battery's cathode is encapsulated within a polymeric matrix that eliminates the exposure hazard posed by lithium intercalation compounds used within the cathode.

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Publication Type: Book
Year of Publication Publication Type Title
2010 Book T. Osaka, Datta, M., and Shacham-Diamand, Y., Electrochemical Nanotechnologies, vol. 1. New York: Springer , 2010, p. 279.[Abstract]

In this book, the term "electrochemical nanotechnology" is defined as nanoprocessing by means of electrochemical techniques. This introductory book reviews the application of electrochemical nanotechnologies with the aim of understanding their wider applicability in evolving nanoindustries. These advances have impacted microelectronics, sensors, materials science, and corrosion science, generating new fields of research that promote interaction between biology, medicine, and microelectronics.

This volume reviews nanotechnology applications in selected high technology areas with particular emphasis on advances in such areas. Chapters are classified under four different headings: Nanotechnology for energy devices - Nanotechnology for magnetic storage devices - Nanotechnology for bio-chip applications - Nanotechnology for MEMS/Packaging.

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2009 Book Y. Shacham-Diamand, Osaka, T., Ohba, T., and Datta, M., Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications. New York: Springer, 2009, p. XX, 552.[Abstract]

Advanced Nanoscale ULSI Interconnects: Fundamental and Applications brings a comprehensive description of copper based interconnect technology for Ultra Large Scale Integration (ULSI) technology to Integrated Circuit (ICs) application. This book reviews the basic technologies used today for the copper metallization of ULSI applications: deposition and planarization. It describes the materials used, their properties, and the way they are all integrated, specifically in regard to the copper integration processes and electrochemical processes in the nanoscale regime. The book also presents various novel nanoscale technologies that will link modern nanoscale electronics to future nanoscale based systems. This diverse, multidisciplinary volume will appeal to process engineers in the microelectronics industry; universities with programs in ULSI design, microelectronics, MEMS and nanoelectronics; and professionals in the electrochemical industry working with materials, plating and tool vendors.

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2004 Book M. Datta, Osaka, T., and J Schultze, W., Microelectronic packaging, 1st ed., vol. 3, 3 vol. CRC press, 2004, p. 564.[Abstract]

Microelectronic Packaging analyzes the massive impact of electrochemical technologies on various levels of microelectronic packaging. Traditionally, interconnections within a chip were considered outside the realm of packaging technologies, but this book emphasizes the importance of chip wiring as a key aspect of microelectronic packaging, and focuses on electrochemical processing as an enabler of advanced chip metallization.

Divided into five parts, the book begins by outlining the basics of electrochemical processing, defining the microelectronic packaging hierarchy, and emphasizing the impact of electrochemical technology on packaging. The second part discusses chip metallization topics including the development of robust barrier layers and alternative metallization materials. Part III explores key aspects of chip-package interconnect technologies, followed by Part IV's analysis of packages, boards, and connectors which covers materials development, technology trends in ceramic packages and multi-chip modules, and electroplated contact materials. Illustrating the importance of processing tools in enabling technology development, the book concludes with chapters on chemical mechanical planarization, electroplating, and wet etching/cleaning tools.

Experts from industry, universities, and national laboratories submitted reviews on each of these subjects, capturing the technological advances made in each area. A detailed examination of how packaging responds to the challenges of Moore's law, this book serves as a timely and valuable reference for microelectronic packaging and processing professionals and other industrial technologists.

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2002 Book W. J Schultze, Osaka, T., and Datta, M., Electrochemical microsystem technologies , 1st ed., vol. 2, 3 vol. Taylor & Francis, 2002, p. 592.[Abstract]

Driven by the electronics industry, electrochemical technology has rapidly evolved, finding increasing applications in microelectronics, batteries, sensors, materials science, industrial fabrication, corrosion, microbiology, neurobiology and medicine. Electrochemical Microsystem Technologies provides an overview of the technological status; the development of micropatternings and micro-biosensors; and the applications of micropower with electrochemical microsystems.

This book covers a wide spectrum of issues ranging from fundamental electrochemical processes to their applications in micro- and nanofabrication, microanalyses, microsensing, and their interaction with inorganic surfaces and biological systems. The editors provide comprehensive background to unique processes, such as the technological development of miniaturization, microfabrication, thin film deposition, etching, cleaning, planarization, and silicon processing technologies to introduce a wide range of applications in context.

More than 40 internationally recognized industry, research, and medical experts provide insight on the current status and future trends in their fields. They also highlight the impact of applying electrochemical microsystem technologies on industries such as storage and packaging; microelectronics, sensors, and portable electronics; machining, polishing, anodization, and plating technologies in heavy industries; biosensing, biological implant technology, and neurobiology; and cross-disciplinary integrated systems.

Electrochemical Microsystem Technologies is a valuable reference for graduate/postgraduate students, technologists, and researchers working in the field of electrochemical technology.

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2000 Book T. Osaka and Datta, M., Energy storage systems in electronics, 3 vol. CRC Press, 2000, p. 604.[Abstract]

This volume illustrates the technological advances made in recent years in the development of battery and other energy storage systems. Discussions of present and near future battery technologies are included as well as emerging energy technologies that have the potential to impact on the portable electronics industry in the long term. This text provides a complete overview of the technology status and trends, with a focus on scientific developments, particularly in materials, that have led to technological breakthroughs.

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Publication Type: Book Chapter
Year of Publication Publication Type Title
2010 Book Chapter M. Datta, “Microelectronic Packaging Trends and the Role of Nanotechnology”, in Electrochemical Nanotechnologies, New York: Springer, 2010, pp. 227–253.[Abstract]

The microelectronic packaging industry is undergoing major changes to keep pace with the ever-increasing demands imposed by high performing chips and by end-use system applications. Solutions using advanced materials for microprocessor interconnect scaling and chip package interconnects, novel concepts in heat management systems, and improvements in package substrates continue to drive major packaging efforts. Advances in electrochemical technologies have played an important role in the evolution of such solutions for miniaturization of microelectronic devices and packages. Indeed, since the development of through-mask plating for thin film heads in the1960s and 1970s, an enormous amount of industrial and academic R&D effort has positioned electrochemical processing among the most sophisticated processing technologies employed in the microelectronics industry today [1–4]. Electrochemical processing is perhaps better understood than some of the dry processing technologies used in the microelectronics industry. Compared to other competing dry processing technologies, it has emerged as a more environmentally-friendly and cost-effective fabrication method. Electrochemical processing has, thus, become an integral part of advanced wafer processing fabs and an enabling technology for nanofabrication [5]. As the electronics industry faces the challenges of extending Moore’s law, electrochemical processing is expected to continue to enable further miniaturization of high-performance chip interconnects, packages, and printed circuit boards. Evolving novel approaches to electrochemical processing using nano-materials and nano-fabrication techniques have started to make tremendous impact on further miniaturization of high performance devices and packages. A detailed discussion of different facets of technology advances in electronic packaging is difficult to present in the limited space of this chapter. The current chapter, therefore, makes an effort to capture some of the key developments in microelectronic packaging while highlighting the impact of electrochemical processing. Also included is a brief discussion of some of the foreseeable applications of nano-materials and nano-structures in advanced packaging.

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2009 Book Chapter M. Datta, “Electrodeposition”, in Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications, Shacham-Diamand, Y., Osaka, T., Datta, M., Ohba, T., editors, Springer, 2009, pp. 63–71.[Abstract]

Electrodeposition is the process of cathodic deposition of metals, alloys, and other conducting materials from an electrolyte using an external potential (electric current) for the cation reduction process to occur at the working substrate. The deposition process is also known as electrolytic plating, electroplating, or simply plating. Electrodeposition is widely employed in a variety of applications ranging from coatings for wear and corrosion resistance to nanoscale feature fabrication for ultra-large-scale integration (ULSI). The deposition thickness may vary from few angstroms of uniformly deposited compact films to electroformed structures that are millimeters thick. Compared to competing vacuum deposition processes, electrodeposition has emerged as more environmentally friendly and cost-effective micro/nanofabrication method.

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2009 Book Chapter M. Datta, “Electrochemical processing tools for advanced copper interconnects: an introduction”, in Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications, Shacham-Diamand, Y., Osaka, T., Datta, M., Ohba, T., editors, Springer, 2009, pp. 389–396.[Abstract]

The change from vacuum-deposited aluminum to electroplated copper in 1997 brought about a paradigm shift in interconnect technology and in chip making [1]. Since then, most of the leading chip manufacturers have converted to electroplated Cu technology for chip interconnects. Cu interconnects are fabricated by dual Damascene process which is referred to a metallization patterning process by which two insulator (dielectric) levels are patterned, filled with copper, and planarized to create a metal layer consisting of vias and lines. The process steps consist of laying a sandwich of two levels of insulator and etch stop layers that are patterned as holes for vias and troughs for lines. They are then filled with a single metallization step. Finally, the excess material is removed, and the wafer is planarized by chemical mechanical polishing (CMP). While finer details of exact sequence of fabrication steps vary, the end result of forming a metal layer remains the same in which vias are formed in the lower layer, and trenches are formed in the upper layer. Electroplating enables deposition of Cu in via holes and overlying trenches in a single step thus eliminating a via/line interface and significantly reducing the cycle time. Due to these reasons and due to relatively less expensive tooling, electroplating is a cost-effective and efficient process for Cu interconnects [2, 3]. Compared with vacuum deposition processes, electroplated Cu provides improved super filling capabilities and abnormal grain growth phenomena. These properties contribute significantly to improved reliability of Cu interconnects. With the proper choice of additives and plating conditions, void-free, seam-free Damascene deposits are obtained which eliminates surface-like fast diffusion paths for Cu electromigration.

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2005 Book Chapter M. Datta, “Electrochemical processing technologies and their impact in microelectronic packaging”, in Microelectronic Packaging Edited by J . W . Schultze , T . Osaka , and M . Datta, US: CRC Press, 2005, pp. 3-27.
2005 Book Chapter M. Datta, “ Flip-chip interconnection”, in Microelectronic Packaging Edited by J . W . Schultze , T . Osaka , and M . Datta, CRC Press, 2005, pp. 167-200.
2005 Book Chapter V. Dubin, Simka, H. S., Shankar, S., Moon, P., Marieb, T., and Datta, M., “Electroplating process for cu chip metallization”, in Microelectronic Packaging, Datta, M., Osaka, T., Schultze, J.W., editors, Boca Raton: US: CRC Press, 2005, p. 31.
Publication Type: Magazine Article
Year of Publication Publication Type Title
2008 Magazine Article M. Datta, “Liquid cooling targets advanced microelectronics”, Electronic Products, p. 29, 2008.
2007 Magazine Article M. Datta, “Precision Liquid Cooling Meets Thermal Challenge of Newest Microelectronic Packaging Trends”, Thermal News, Volume 1, issue 1, pp 1-11, Fall 2007., vol. 1, no. 1, pp. 1-11, 2007.
Publication Type: Conference Proceedings
Year of Publication Publication Type Title
2006 Conference Proceedings M. Datta, “Electrochemical Processing Trends in Micro/Nano Electronics”, 8th International Symposium on Magnetic Materials, Processes, and Devices, Honolulu, Hawaii S. Krongelb, C. Bonhote, T. Osaka, Y. Kitamoto, editors, . 2006.
1999 Conference Proceedings S. K. Kang, Horkans, J., Andricacos, P. C., Carruthers, R. A., Cotte, J., Datta, M., Gruber, P., Harper, J. M. E., Kwietniak, K., Sambucetti, C., Shi, L., Brouillette, G., and Danovitch, D., “Pb-free solder alloys for flip chip applications”, Proceedings of 49th Electronic Components and Technology Conference, 1999. IEEE, San Diego, CA, pp. 283 - 288, 1999.[Abstract]

In addition to the environmental issue regarding the use of Pb-bearing solders in microelectronics applications, there is another issue associated with using Pb-bearing solders in interconnections, like flip chip solder interconnections in an advanced CMOS technology, that are near active circuits. In order to minimize the soft error rate due to alpha particle emission from Pb-bearing solder alloys, Pb-free solder alloys were studied as possible replacements for the Pb-based solders that are presently used in flip chip interconnections. A large number of solder compositions was selected for evaluation. Since all the candidate alloys were Sn-based, alternatives for the ball-limiting metallurgy (BLM) were also investigated. The physical, chemical, mechanical and electrical properties of the alloys were determined by thermal analysis, wettability testing, microhardness measurement, electrical resistivity measurement, interfacial reaction study and others. Test vehicles were also built with some selected Pb-free solder alloys with the proper BLM to evaluate integrity of the flip chip solder bump structure. Based on this study, a few candidate solder alloys were selected with a proper BLM barrier layer for flip chip applications

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Pages

Peer Reviewed International Journals (Under Review)

  1. Datta, M., Bonded Ceramic-Metal Layers for fabrication of Thermal Conduction Plates, submitted for publication in J. Materials Processing technollogy (under review); IF: 2.041
  2. Datta, M., Choi, H.W., Microheat Exchanger for Cooling High Power Laser Diodes, submitted for publication in J. Appld. Thermal Engineering (under Review); IF: 2.88
  3. Datta, M., Microfabrication by High rate Anodic Dissolution: Fundamentals and Applications, to be submitted in JECS; IF: 2.859

Reviewer – Journals and Conferences

  1. Electrochmica Acta, 2. J. Electrochemical Society, 3. J. Applied Electrochemistry, 4. Surface Science, 5. Corrosion Science, 6. Micro Nanosystems; 7. Numerous international conferences.

Conferences – Organized

  1. Datta, M., Symposium Organizer, Processing of Electronic Materials by Wet Etching NEPCON-West, Anaheim, CA, Feb-March 1990.
  2. Datta, M., Symposium Organizer, Electrochemical Microfabrication I, ECS Fall Meeting, Phoenix, October 1991
  3. Datta, M., Symposium Co-organizer, Electrochemical Technology Applications in Electronics, Spring Meeting, Honolulu, May 1993 (Symposium Co-Chair)
  4. Datta, M., Symposium Organizer, Electrochemical Microfabrication –II, ECS Meeting, Miami Beach, Florida, October 1994.
  5. Datta, M., Symposium Organizer, High Rate Metal Dissolution Processes, ECS Fall Meeting, Chicago, October 1995.
  6. Datta, M., Symposium Co-organizer, First International Symposium on Electrochemical Microsystem Technologies, Düsseldorf, August 1996.
  7. Datta, M., Symposium Organizer, Environmental Aspects of Electrochemical Technology: Applications in Electronics, ECS Fall Meeting San Antonio, October 1996.
  8. Datta, M., Symposium Co-organizer, Fundamental Aspects of Electrodeposition and Dissolution including Modeling Joint ECS/ISE Meeting, Paris, August/September 1997
  9. Datta, M., Symposium Co-organizer, Second International Symposium on Electrochemical Microsystem Technologies, Tokyo, September 1998
  10. Datta, M., Symposium Co-organizer, Electrochemical Technology in Microelectronics, ISE Meeting, Kitakyushu, Japan, September 1998
  11. Datta, M., Symposium Co-organizer, Applications of Electrochemical technology in the Electronics Industry, , 2001 Joint ECS/ISE Meeting San Francisco, September 2-7, 2001.
  12. Datta, M., Symposium Organizer, Symposium in honor of Dr. L.T. Romankiw, ECS Fall Meeting, Honolulu, Hawaii, October 2004.

Other Academic/Non-Academic Activities

Offices held in Professional Societies

  • 1999-2000: Chairman, Electrodeposition Division, Electrochemical Society, NJ.
  • 1997-1999; Treasurer/Secretary, electrodeposition division, Electrochemical Society, NJ
  • 1995-1997; Member, Ways and means committee, Electrochemical Society, NJ
  • 1997-1998: Chairman, Corrosion, Electrodeposition and surface treatment Division, International Society of Electrochemistry
  • 1994-1996: Co-chairman, Corrosion, Electrodeposition and surface treatment Division, International Society of Electrochemistry
  • 1992-1994: Councilor, Metropolitan NY Section of Electrochemical Society, NJ
  • 1991-1994: North American Editor, Processing of Advanced Materials, Chapman and Hall
  • 1991-1992: Chairman, Metropolitan NY Section of Electrochemical Society, NJ
  • 1990-1991: Vice Chairman, Metropolitan NY Section of Electrochemical Society, NJ
     

Major Accomplishments (Projects/Products)

  • Developed Liquid Cooling Systems for Apple’s Power Mac G5 Desktops (Cooligy)
  • Developed Micro-heat Exchangers for High Power Laser Diodes (Cooligy).
  • Developed Advanced Joining Materials and Techniques for manufacturing reliability of Data Center Cooling components (Cooligy).
  • Developed strategic directions for Lead-free, compliant Flip-Chip Technology (Intel).
  • Managed Passivation/C4 Fab operations including move to 300 mm wafers (Intel).
  • Developed electroless and electrolytic Cu deposition processes for seed layer and chip interconnects (Intel).
  • Conceived, Developed, and Transferred to IBM manufacturing the electroplated C4 (flip-chip) technology.  The plated C4 technology is now an industry standard advanced chip-package interconnection (IBM).
  • Invented and built a unique electroetching process/tool for removal of thin metal layers from wafers and demonstrated its applicability in the fabrication of C4s.    The electroetching tool is now marketed by Semitool under license from IBM (IBM).
  • Developed thin foil-type, flexible primary batteries for Smart Cards and RF-ID Tags (IBM).
     

Interactions with Universities

  • 1996-present: Working with Prof. Tetsuya Osaka of Waseda University, Tokyo on electrochemical processing related activities, editing books on these topics.
  • 1991 to 1999:  Adjunct Professor, Department of Chemical Engineering, University of Connecticut, Storrs, CT.
  • Co-directed graduate research work of: S-J. Jaw (Ph.D., 1996, UCONN), L.F. Vega (Ph.D., 1990, Columbia), and M. Kurdziel (M.S. 1991, Columbia),
  • 1987-1999: Developed collaboration between IBM and Universities in the NY metropolitan tri-state area in the field of electrochemical processing technologies. Coordinated and Mentored IBM’s SUR (shared university research) projects with Columbia University, NY, and Stevens Institute of Technology, NJ.
  • 1975 to 1984:  Taught Corrosion Science (with lab) and supervised graduate research, Chemical Metallurgy Lab, Swiss Federal Institute of Technology, Lausanne, Switzerland
     

PROFESSIONAL ACTIVITIES/ HONORS

Awards/ Honors

  • 1998 Electrodeposition Research Award of the Electrochemical Society.
  • Ninth Plateau of IBM Invention Achievement Awards.
  • IBM’s Top 5% Patent award
  • Inventor of 48 issued US patents, 9 IBM Technical Disclosure Bulletins.
  • Author of 80+ scientific papers and author/editor of several books on Electrochemical Processing & Microelectronic Packaging.
  • Organizer of International symposia; Keynote and Invited speaker.  
  • Member, IBM Technical Strategy Assessment Team for development of Low Power Technical Strategy for portable computing.
  • Chaired the Technology Working Group and Technology Implementation Group of National Electronic Manufacturing Initiative (NEMI) and developed a first of its kind technology roadmap of energy storage systems for the electronics industry.  Awarded NEMI’s leadership certificate.
  • Included in 2000 outstanding scientists of the 20th Century in honor of outstanding contribution in the field of Electrochemical Microfabrication, International Biographical Center, Cambridge, England, 1998.
     

Symposium Organizer/ Co-organizer

  • Symposium Organizer, Processing of Electronic Materials by Wet Etching NEPCON-West, Anaheim, CA, Feb-March 1990. 
  • Symposium Organizer, Electrochemical Microfabrication I, ECS Fall Meeting, Phoenix, October 1991
  • Symposium Co-organizer, Electrochemical Technology Applications in Electronics,  Spring Meeting, Honolulu, May 1993 (Symposium Co-Chair)
  • Symposium Organizer, Electrochemical Microfabrication –II, ECS Meeting, Miami Beach, Florida, October 1994.
  • Symposium Organizer, High Rate Metal Dissolution Processes, ECS Fall Meeting, Chicago, October 1995.
  • Symposium Co-organizer, First International Symposium on Electrochemical Microsystem Technologies, Düsseldorf, August 1996.
  • Symposium Organizer, Environmental Aspects of Electrochemical Technology: Applications in Electronics, ECS Fall Meeting San Antonio, October 1996.
  • Symposium Co-organizer, Fundamental Aspects of Electrodeposition and Dissolution including Modeling Joint ECS/ISE Meeting, Paris, August/September 1997
  • Symposium Co-organizer, Second International Symposium on Electrochemical Microsystem Technologies, Tokyo, September 1998
  • Symposium Co-organizer, Electrochemical Technology in Microelectronics,  ISE Meeting, Kitakyushu, Japan, September 1998
  • Symposium Co-organizer, Applications of Electrochemical technology in the Electronics Industry, , 2001 Joint ECS/ISE Meeting San Francisco, September 2-7, 2001.  
  • Symposium Organizer, Symposium in honor of Dr. L.T. Romankiw, ECS Fall Meeting, Honolulu, Hawaii, October 2004.
     

Key International Conferences (Invited Speaker/Symposium Chair/Keynote speaker)

  • Invited Speaker.  Application of Chemical and Electrochemical Micromachining in the Electronics Industry, ECS Fall Meeting, Honolulu, Hawaii, October 1987.
  • Invited Speaker. Laser Chemical Etching of Metals in Neutral Salt Solutions, MRS Symposium, Boston, December 1987.
  • Invited Speaker. Microfabrication by Electrochemical Machining, Intl. Microelectronics Conference, ISHM, Tokyo, May 1988.
  • Invited Speaker. Challenges in Electrochemical Machining Related to Surface Preparation,  NEPCON-West, Anaheim, CA, March 1989.
  • Invited Speaker. High Speed Maskless Patterning by Electrolytic Jet, AIChE Meeting San Francisco, November 1989.
  • Keynote Speaker and Symposium Chair. Processing of Electronic Materials by Wet Etching NEPCON-West, Anaheim, CA, Feb-March 1990. 
  • Keynote Speaker and Session Chair, Microfabrication by Electrodissolution, ISE meeting, Montreaux, Switzerland, August, 1991
  • Invited Speaker, Electrochemical fabrication of V-shaped nozzles for high speed printers,   Electrochemical Microfabrication I, ECS Fall Meeting, Phoenix, October 1991
  • Invited Speaker. Transport Processes During High Rate Dissolution of Metals, AIChE Meeting, Miami Beach, Florida, November 1992
  • Invited Speaker, Selective Material Removal by Wet Etching: Applications in Microfabrication, INCOSURF-92, Bangalore, December 1992
  • Invited Speaker and Session Chair, Through-Mask Electrochemical Micromachining of Thin Films ECS Spring Meeting, Honolulu, May 1993 (Symposium Co-Chair)
  • Keynote Speaker, Recent Advances in the Study of Electrochemical Micromachining, ASME Symposium on Non-Traditional Machining, Nov-Dec 1993
  • Invited Speaker, Electrochemical fabrication of mechanically robust C4s,  Electrochemical Microfabrication –II, ECS Meeting, Miami Beach, Florida, October, 1994.
  • Keynote Speaker and Session Chair, Electrochemical Micromachining in the Electronics Industry, ISE Meeting, Xiamen, China, September, 1995.
  • Keynote Speaker and Session Chair, First International Symposium on Electrochemical Microsystem Technologies, Düsseldorf, August 1996.
  • Keynote Speaker, Microfabrication by Through-Mask Electrochemical Micromachining, International Society for Optical Engineering (SPIE) meeting, Austin, September 1997.
  • Keynote Speaker and Session Chair, Maskless and Through-Mask Electrochemical Micromachining, Second International Symposium on Electrochemical Microsystem Technologies, Tokyo, September 1998
  • Electrodeposition Div. Research Award Lecture, Electrodissolution Processes: Fundamentals and Application in Microelectronics, ECS Fall Meeting Boston, November 1998.
  • Keynote Speaker and Session Chair, Electrochemical Processing Technologies in Chip Fabrication: Challenges and Opportunities, ISE Meeting, Düsseldorf, Germany, September 2002
  • Keynote Speaker, Paradigm Shifts in Microelectronics: The Role of Electrochemical Processing, Peaks in Plating, An International Symposium on Electrochemical Processes and Tools, Organized    by SemiTool, sponsored by Electrochemical Society, Semiconductor International, September 2004.
  • Invited Speaker and Session Chair, Electrochemical Processing Trends in Micro/Nano Electronics, ECS Fall Meeting, Honolulu, Hawaii, October 2004
  • Invited Speaker, Electrochemical Processing in Microelectronics, Talk presented at December 14, 2005 meeting of Santa Clara Valley Chapter of ASM International.
  • Invited Speaker, Liquid Cooling System for Advanced Microelectronics, ECS Spring Meeting, Symposium on ULSI & MEMS, Chicago, May 2007.
  • Invited Speaker, Advanced Cooling Solutions for High Power Laser Diodes and IGBTs, Thermal Management & Technology Symposium, October 20-21, 2009, Denver, Colorado. 
  • Keynote Speaker, Microfabrication by High rate Anodic Dissolution: Fundamentals and Applications, Symposium on High Rate Metal Dissolution Processes 2, 227th ECS meeting, Chicago, May 24-28, 2015.
     

IBM Technical Disclosure Bulletin

  • M. Datta, L.T. Romankiw, D.R. Vigliotti, R.J. von Gutfeld; Laser-jet Electrochemical Micromachining in Neutral Chloride Solution; Y08880092, IBM Technical Disclosure Bulletin, volume 32, 3A, August 1989, pp109-110.
  • M. Datta, S. Krongelb, L.T. Romankiw; Selective Etching of Cu; Y08870724, IBM Technical Disclosure Bulletin, volume 32, n11,  April August 1990, pp 231-232.
  • B. Braren, M. Datta, D. Vigliotti, R.J. von Gutfeld; One-Step Mask Making; Y08870623, Research Disclosure,  n317, September 1990.
  • B. Bumble, C. Clerc, M, Datta, R.L. Sandstorm; A Movable Multilevel Metal Mask for Depositing High temperature Super Conducting Oxide Films and Barrier Layers; Y08890355, Research Disclosure, n337, May 1992.
  • M. Datta; Fabrication of Ink-jet Printer Head Components by Through-Mask Electrochemical Micromachining, Y08910623, IBM Technical Disclosure Bulletin, volume 35, n1B, June 1992, pp453-454.
  • I-C.H. Chang, M. Datta, G.S. Frankel, W.J. Horkans; Cleaning Process for Cu(P) Anodes; Y08920123, Research Disclosure,  n344, December 1992.
  • M.J. Brady, M. Datta, P.A. Moskowitz, R.V. Shenoy; Battery Lead Configuration for Efficient Footprint Utilization, Y08940315, IBM Technical Disclosure Bulletin, volume 38, no 12, December 1995, pp 247-248.
  • E.I. Cooper, M. Datta, R.V. Shenoy, E. Tierney; Method to Monitor and Control Boil-over of Hydrogen Peroxide Based Solutions; Y08940505, IBM Technical Disclosure Bulletin, volume 38, no 12, December 1995, pp 417-418.
  • J. Cotte, M. Datta, L. Shi; Reflow of Electrochemically Fabricated C4s using Glycerol-based Water Soluble Flux; Y08940298, IBM Technical Disclosure Bulletin, volume 39, no 7, July 1996.
     

Membership in Professional Bodies

  1. International Society of Electrochemistry (ISE), Active Member
  2. Electrochemical Society, NJ, Active member
     

Student Guidance

Doctoral Students

  • “Anodic Dissolution of Iron and 304 Stainless Steel in Phosphoric Acid based solutions.”, Luis Fanor Vega, received Sc. D. degree from the School of Engineering and Applied Science, Columbia University, 1990 (The doctoral thesis work was conducted at IBM under the guidance of M. Datta, with Prof. P. Duby as the Co-guide from Columbia University).
  • “High Rate anodic Dissolution and Jet Electrochemical Micromachining of Tungsten”, Shyh-Jin Jaw, Ph.D. degree from Chemical Engineering Department, University of Connecticut, 1996 (M. Datta acted as co-advisor with Prof. James Fenton of UCONN).
     

Master’s Students

  • “AES/XPS Study of Transpassive Films on Molybdenum in Sulfate Solutions”, Mathew Thomas Kurdziel, Thesis in fulfillment of Master of Engineering degree from the School of Engineering and Applied Science, Columbia University, 1991 (The MS thesis work was conducted at IBM under the guidance of M. Datta, with Prof. P. Duby as the Co-guide from Coulmbia University
     

Others

  • North American Editor, Processing of Advanced Materials, Chapman and Hall, 1991-1994.
  • Advisory Board, Journal of Materials Processing Technology, Elsevier. 1995-1999.
  • Guest Editor, Special Issue of Processing of Advanced Materials devoted to Environmental Aspects, Volume 4, No. 4, Chapman and Hall, 1994.
  • Guest Editor, Special issue of IBM Journal of Research and Development devoted to Electrochemical Microfabrication, Volume 42, No. 5, September 1998.

 

Faculty Details

Qualification:

Designation: 
Faculty Email: 
madhavdatta@amrita.edu