Mamatha I. currently serves as Assistant Professor(Sr.Gr) at department of Electrical & Electronics, Amrita School of Engineering, Banglore campus. She is currently pursuing her Ph. D. 






Publication Type: Conference Paper
Year of Publication Publication Type Title
2015 Conference Paper I. Mamatha, Raj, J. N., Tripathi, S., and T.S.B. Sudarshan, “Systolic architecture implementation of 1D DFT and 1D DCT”, in 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015, 2015.[Abstract]

Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement, OFDM etc. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT, a unified architecture is proposed for 1D DFT/1D DCT. © 2015 IEEE.

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2015 Conference Paper S. V. B. Bala Sai, Mamatha, I., Tripathi, S., and Sudarshan, T. S. B., “Modified MLBF based architecture for 1-D DWT”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai,India, 2015.[Abstract]

This work proposes an architecture for fast computation of 1-D Discrete Wavelet Transform (DWT). Existing MAC loop based filter (MLBF) is modified and a poly-phase structure for 1-D DWT is proposed. Proposed structure improves the throughput by 1.5x while using almost double the hardware as that of the existing structure. 1-D DWT using existing MLBF structure and proposed structure are simulated using ModelSim and synthesized using Xilinx ISE 14.2 on Virtex-6 XC6VCX240T-2FF784 target device. It is observed that the proposed architecture can be operated at a maximum frequency of 163.59MHz. The simulation results obtained from ModelSim is compared with MatLab R2010a output and found to be accurate. More »»
Publication Type: Journal Article
Year of Publication Publication Type Title
2015 Journal Article I. Mamatha, T.S.B. Sudarshan, Tripathi, S., and Bhattar, N., “Triple-Matrix Product-Based 2D Systolic Implementation of Discrete Fourier Transform”, Circuits, Systems, and Signal Processing, vol. 34, pp. 3221–3239, 2015.[Abstract]

Realization of N -point discrete Fourier transform (DFT) using one-dimensional or two-dimensional systolic array structures has been developed for power of two DFT sizes. DFT algorithm, which can be represented as a triple-matrix product, can be realized by decomposing N into smaller lengths. Triple-matrix product form of representation enables to map the N -point DFT on a 2D systolic array. In this work, an algorithm is developed and is mapped to a two-dimensional systolic structure where DFT size can be non-power of two. The proposed work gives flexibility to choose N for an application where N is a composite number. The total time required to compute N -point DFT is 2 ( N 1 - 1 ) + N 2 + N for any N = N 1 N 2 . The array can be used for matrix–matrix multiplication and also to compute the diagonal elements of triple-matrix multiplication for other applications. The proposed architecture produces in-order stream of DFT sequence at the output avoiding need for reordering buffer. Large sized DFT can be computed by repeatedly using the proposed systolic array architecture. More »»
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