Qualification: 
M.Tech
n_kayalvizhi@cb.amrita.edu
Phone: 
+91 422 2685000 Ext. 5727

Kayalvizhi N. joined Amrita School of Engineering in the year 2003. She completed her Bachelor’s degree in Electronics and communication Engineering from Amrita Institute of Technology, Coimbatore, India , in the year 2002 and Master’s in MicroElectronics and VLSI Design from NIT Calicut, India. She is pursuing her Ph.D in the field of Biomedical and Instrumentation. Her current research interests include Biomedical instrumentation and signal processing.

Education

  • Pursuing: Ph. D. in Biomedical Instrumentation
    Amrita Vishwa Vidyapeetham
  • 2006 - 2008 : Masters in Micro Electronics and VLSI Design
    NIT Calicut
  • 2002: Bachelor’s Degree in Electronics and Communication Engineering
    Amrita Vishwa Vidyapeetham

Professional Experience

Year Affiliation
2008 - Till Present Assistant Professor (Sr. Gr.), Amrita Vishwa Vidyapeetham
Domain : Teaching, Research and Projects Dept Administration
2005 - 2008 Assistant Professor, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research and Projects Dept Administration
2003 - 2005 Lecturer, Amrita Vishwa Vidyapeetham
Domain : Teaching, Dept Administration

Academic Responsibilities

SNo Position Class / Batch
1. Class Adviser 2015 - 19
2. Academic Coordinator 2015-2019

Undergraduate Courses Handled

  1. Digital Systems
  2. Electronics Circuits
  3. Linear Integrated Circuits
  4. Solid State Devices
  5. Network Theory

Post-Graduate / PhD Courses Handled

  • Biomedical Instrumentation.

Organizing Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. BiSac Amrita Vishwa Vidyapeetham December 17-19 2015 Familiarized the participants with hardware circuits for acquiring Biomedical Signals.

Academic Research – PG Projects

  1. Amrutha Paul- comparison of parallel summation and weak inversion based logarithmic amplifier.
  2. Paulcy Paul A 4.2ppm/°C Temperature Compensated CMOS Voltage Reference
  3. Nitha Mathew -A 2.89ppm/°C Current Reference Generation with Temperature Compensation using 90-nm CMOS Circuit
  4. TheerthaAbhayEstimating Correlation between Arterial Blood Pressure and Photoplethysmograph
  5. Lakhsmi Mukundan- PTT calculation from ECG and PPG

Publications

Publication Type: Conference Proceedings

Year of Publication Title

2017

M. Lokharan, Kumar, K. C. Lokesh, V. Kumar, H., Kayalvizhi, N. M. N., and Aryalekshmi, R., “Measurement of Pulse Transit Time (PTT) using Photoplethysmography”, The 16th International Conference on Biomedical Engineering. IFMBE Proceedings, vol. 61. Springer Verlag, pp. 130-134, 2017.[Abstract]


An experimental setup for measuring pulse transit time (PTT) using two photoplethysmographic (PPG) signals is proposed. The pulse wave velocity is calculated from the measured PTT, for its potential use in monitoring arterial stiffness and continuous non-invasive arterial blood pressure. The PPG sensors are placed in-line separated by 1cm, over the arterial branch under consideration. PTT is determined by using the fact that there exists a time difference be-tween PPG signals obtained from the two sensors. The outputs from the sensors are bandlimited and amplified. The signals are then made TTL- compatible, to determine pulse transit time. The final output is in the form of a rectangular pulse whose width is equal to the PTT. A phase shifted sinusoid generated by an all-pass filter is used to validate the proposed experimental setup. Placing the sen-sors over the digital artery of the index finger, 1 cm apart, the PTT for 13 healthy volunteers was measured. PTT is averaged for 10 cardiac cycles to obtain mean PTT. From mean PTT the Pulse Wave Velocity (PWV) is calculated for a volunteer. The maximum of 2.6 and a minimum of 0.4 standard deviation was observed, for a single volunteer. The overall mean PTT was 10.1 ms and the mean PWV was 1.1 m/s.

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2017

T. Abhay, Kayalvizhi, N. M. N., and J. Gini, R., “Estimating Correlation between Arterial Blood Pressure and Photoplethysmograph”, The 16th International Conference on Biomedical Engineering. IFMBE Proceedings, vol. 61. Springer Verlag, pp. 47-52, 2017.[Abstract]


Photoplethysmograph (PPG) and Arterial Blood Pressure (ABP) are good indicators of cardiovascular performance. Although ABP is more widely employed, the invasive procedure of signal acquisition may cause skin rashes and inconvenience to the patients. Also, it does not allow continuous monitoring of cardiac activity. PPG, on the other hand, uses infrared light to measure the blood volume changes, which is a simple, noninvasive and can be used for continuous measurement. This paper focuses on analyzing the similarity between ABP and PPG using various features like average slope, peak position, time period, elasticity, amplitude of the signal. A segmentation algorithm was used to segment out cycles of ABP and PPG from physionet database taken from 19 patients with respiratory failure and the values of each feature were extracted for each person. Considering the population, using Pearson’s correlation coefficient, the coefficient for the average slope of the PPG and peak to peak amplitude of ABP was found to be 0.55 indicating that other factors such as vessel diameter, thickness must be considered. The upstroke time period of both ABP and PPG was found to have a small difference in the range of 0.02s to 0.1s, whereas the time period of the heart cycles remained the same irrespective of the disease or healthy condition. The peak value of both ABP and PPG was found to occur with constant time difference. The elasticity with peak to peak amplitude of ABP was found to have a correlation of 0.822, and with systolic blood pressure, a correlation of 0.7622. When considered for individuals, parameters like the diastolic average slope of PPG and systolic blood pressure were found to have a good correlation coefficient ranging from 0.6 to 0.96 among other parameters which include systolic average slope, maximum and minimum slope of PPG, and the diastolic blood pressure.

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Publication Type: Journal Article

Year of Publication Title

2015

N. M. N. Kayalvizhi and Mathew, N., “A 2.89ppm/°C Current Reference Generation with Temperature Compensation using 90-nm CMOS Circuit”, International Journal of Applied Engineering Research , vol. 10, no. 12, pp. 32363-32369, 2015.[Abstract]


This paper presents a low-power and low-voltage CMOS based reference current system, stable against temperature variation using 90 nm CMOS technology. Comparatively less power consumption of 2.02 μW is achieved by the circuit. The circuit is intended to compensate the variation in threshold voltage and mobility of MOSFETs with temperature. MOSFETs in this circuit are biased at their ZTC point to achieve temperature compensation and the circuit generates a reference current that is compensated against temperature variation. It attains a temperature coefficient of 2.89 ppm/°C for a drift of 20°C to 160°C.

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2015

P. Paul and Kayalvizhi, N. M. N., “A 4.2ppm/°C temperature compensated CMOS voltage reference”, International Journal of Applied Engineering Research, vol. 10, pp. 23739-23746, 2015.[Abstract]


A voltage reference circuit compatible with latest CMOS standards and temperature stability was developed using 90nm CMOS technology. The circuit includes CMOS transistors operating in saturation and triode regions, without the aid of resistors, diodes and bipolar transistors. In a band gap voltage reference circuit, the temperature independent reference voltage is attained by the base emitter voltages of the bipolar transistors used. In the proposed circuit these bipolar transistors and resistors are replaced by ratioed MOS transistors. The CMOS transistors were biased and designed in such a way that the temperature dependencies of mobility and gate oxide were nullified. The circuit was developed for a constant reference voltage of 1.03V with a temperature coefficient of 4.2ppm/°C, over a range of 0-160 °C. The circuit was operated with a supply voltage of 1.8V and draws a maximum value of supply current as 9.05μA and maximum power dissipation was 77.73μW. © Research India Publications.

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2014

N. M. N. Kayalvizhi, “Comparison of Parallel Summation and Weak Inversion Based Logarithmic Amplifier”, International Journal of Research in Engineering and Technology (IJRET), vol. 3, no. 24, pp. 1-5, 2014.[Abstract]


Logarithmic amplifier is used for reducing the dynamic range of the input signal. Logarithmic amplifier is implemented using two different techniques. One of the methods is a parallel summation based method and the other one is a weak inversion based method. In parallel summation based method the transistors are maintained in saturation whereas in weak inversion based method the transistors are maintained in weak inversion. Both methods are simulated in 50nm CMOS technology using HSPICE. Considering power, area and dynamic range weak inversion method is more efficient compared to parallel summation method.

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2012

N. M. N. Kayalvizhi, “Implementation of Power Efficient Vedic Multiplier”, International Journal of Computer Applications, vol. 43, no. 16, 2012.[Abstract]


Vedic multiplier is based on the ancient algorithms (sutras) followed in INDIA for multiplication. This work is based on one of the sutras called "Nikhilam Sutra". These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes more power than the conventional ones. This paper presents a technique to modify the architecture of the Vedic multiplier by using some existing methods in order to reduce power. The 32 X 32 Vedic multiplier is coded in Verilog HDL and Synthesized using Synopsys Design Compiler. The performance is compared in terms of area, data arrival time and power with earlier existing architecture of Vedic multiplier. The proposed design shows very good improvements in terms of power. More »»

2012

C. S. Shari Jahan and Kayalvizhi, N. M. N., “Adiabatic technique for designing energy efficient logic circuits”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 100-107, 2012.[Abstract]


Energy minimization is an important factor in designing digital circuits which are portable and battery operated.Irreversible logic operation causes the minimum dissipation of KT ln 2 joules of heat energy when each bit is erased.Reversible logic that employs adiabatic switching principles can be used to minimize dynamic power , which is the major contributor to total power dissipation. Reversible Energy Recovery Logic (RERL) belongs to fully adiabatic logic family and it eliminates non adiabatic energy loss by making use of reversible logic. RERL NAND/AND gate and RERL SR latch is proposed in this work using eight phase clocking scheme. This RERL circuits consume less energy compared with static CMOS logic circuits at low speed operation. The simulation result using HSPICE shows that RERL circuits consume less power compared with the static CMOS circuits. © 2012 Springer-Verlag.

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2011

S. S. Sakthi and Kayalvizhi, N. M. N., “Power Aware Reconfigurable Multiplier for DSP Applications”, International Journal of Computer Science & Engineering Technology (IJCSET), vol. 1, no. 5, pp. 234-237 , 2011.[Abstract]


DSP applications are rich in multiplication operations. Hence there is a growing need in improving the efficiency of multipliers. To improve the performance of multipliers, reconfiguration is introduced. In this paper, reconfiguration is introduced in the form of one level recursive architecture to the existing modified booth multiplier (MBM). It provides reconfigurable modes that satisfy multiple precision requirements. Power consumption of the multipliers can be reduced with the introduction of power efficient schemes namely Dynamic Operand Interchange and Spurious Power Suppression Technique to the reconfigurable booth architecture. More »»

2010

A. Raj and Kayalvizhi, N. M. N., “High throughput multipliers using delay equalization”, International Journal of Computer Applications , vol. 2, 2010.

Publication Type: Conference Paper

Year of Publication Title

2011

S. S. Sakthi and Kayalvizhi, N. M. N., “Power aware and high speed reconfigurable modified booth multiplier”, in 2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, Trivandrum, Kerala, 2011, pp. 352-356.[Abstract]


Multiplier is one of the major arithmetic operations carried out in DSP applications. Multiplier architecture is reconfigured so as to enhance their performance and thereby improving the efficiency of the applications. This Reconfigurable multiplier is adapted at run time to satisfy multiple precision requirements of DSP applications. Power consumption of the multipliers is reduced with the introduction of power efficient scheme Dynamic Operand Interchange to the reconfigurable booth architecture. Implementation is done in Verilog and simulated using MODELSIM. Power and Timing analysis is done using Altera Quartus II tool (version 9.0) © 2011 IEEE.

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2009

G. C. V., Kayalvizhi, N. M. N., and M., M., “Generation of New March Tests with Low Test Power and High Fault Coverage by Test Sequence Reordering Using Genetic Algorithm”, in Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on, 2009.