Qualification: 
Ph.D, MBA
ns_murty@blr.amrita.edu

Dr. N. S. Murty serves as Chairperson and M.Tech. Coordinator at the department of Electronics and Communication, Amrita School of Engineering, Bengaluru. His areas of research include VLSI technology and design, Green energy harvesting. He has also completed MSc (Tech) and MSB.

Education

  • 2002: Mastering Semiconductors Business (MSB)
    Ashridge Management College, UK
  • 1996: MBA
    IGNOU, Delhi
  • 1983: Ph. D. 
    IIT, Bombay

Publications

Publication Type: Journal Article

Year of Publication Publication Type Title

2018

Journal Article

M. Vinodhini and Dr. N.S. Murty, “Reliable low power NoC interconnect”, Microprocessors and Microsystems, vol. 57, pp. 15-22, 2018.[Abstract]


Information communicated through Network on Chip (NoC) in System on Chip (SoC) is highly prone to different sources of noise, like coupling, radiation and electromagnetic interference. The outcome is multi-bit errors, which can either be random or burst. As the demand for reliable NoC increases, optimal error correcting coding techniques become imperative for SoC and various multi-core and many-core architectures. A novel Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB) is proposed to achieve reliable data transmission through NoC. The proposed technique corrects burst error of four bits or random error of eleven bits or combined burst and random errors of total four bits for an input flit size of 32 bits. Analytical model based performance estimation for coding technique is extensively used in NoC. Reliability, link swing voltage and link power consumption are estimated using analytical model for the proposed MECCRLB coding technique. All the results obtained for MECCRLB coding technique are compared with Hamming product code with Type II HARQ. Estimated results show that at a probability of residual error of 10−25, the link swing voltage and the link power are reduced by 30% and 75% respectively. Results obtained from simulation followed by synthesis indicate that there is a reduction of 65%, 44%, 27%, 28% and 49% in bit overhead, NoC router area, NoC router power, codec power and codec area respectively. Furthermore, MECCRLB coding technique achieves higher error correction capability and reduces the need for retransmission. This signifies that the proposed coding technique outperforms Hamming product code with Type II HARQ in reliability, area and power. © 2017 Elsevier B.V. More »»

2018

Journal Article

K. Vrinda, Dr. N.S. Murty, and Dr. Dhanesh G. Kurup, “Performance of Vector Fitting Algorithm Applied to Bandpass and Baseband Systems”, Circuits, Systems, and Signal Processing, 2018.[Abstract]


This article presents the performance evaluation of Vector Fitting Algorithm (VFA) from a system identification perspective. In this paper, VFA has been first applied to known baseband and bandpass systems such as Butterworth lowpass and bandpass filters to analyze the algorithm's pole-residue extraction ability for band-limited noisy data. The poles identified by the algorithm for different bandwidths and noise powers are compared with the actual system poles of the baseband and bandpass systems. It is concluded that the algorithm is capable of identifying the actual system poles even if the capture bandwidth is less than the 3 dB bandwidth, which is a significant observation of this paper. It is also seen that the system identification performance with noisy data is better for baseband systems when compared to bandpass systems. Further, a practical investigation has been done to evaluate VFA performance for modeling a microstrip coupled line filter in the presence of noise. More »»

Publication Type: Conference Paper

Year of Publication Publication Type Title

2017

Conference Paper

P. Raha, M. Vinodhini, and Dr. N.S. Murty, “Horizontal-vertical parity and diagonal hamming based soft error detection and correction for memories”, in 2017 International Conference on Computer Communication and Informatics (ICCCI), 2017.[Abstract]


External radiations create soft errors which are turning into an undeniable critical issue. Customarily, Single Error Correction (SEC) code which can detect and correct 1-bit error per memory word is used to rectify soft errors. As errors turn out to be more common, the SEC methodology becomes inefficient. In this paper, Horizontal-Vertical Parity and Diagonal Hamming (HVPDH) method is proposed for detection of up to 8-bit errors and correction of 1-bit error, all combinations of 2-bit errors and most combinations of 3, 4 and 5-bit errors for memories. The aim here is to incorporate an encoder and decoder which will be effective in detecting and correcting errors. The encoder and decoder use three parity sets, namely horizontal, vertical and grouped diagonal Hamming parities. As per the analysis, higher code rate is achieved by using HVPDH method in memories when compared to the existing methods. More »»

2017

Conference Paper

S. Tambatkar, Menon, S. N., Sudarshan, V., M. Vinodhini, and Dr. N.S. Murty, “Error detection and correction in semiconductor memories using 3D parity check code with hamming code”, in 2017 International Conference on Communication and Signal Processing (ICCSP), 2017.[Abstract]


Data stored in memory or buffer needs Error Detection And Correction (EDAC). Errors occur due to supply voltage fluctuations and/or noise due to electromagnetic interference or external radiation. These errors could be either temporary or permanent. In this paper, a EDAC method is proposed to detect and correct errors based on 3D parity check. In the encoder, the data bits are arranged in a matrix format and then parity bits are calculated for each row, column and diagonal. Errors present in parity bits are detected and corrected using Hamming code. Regeneration of data bits and Syndrome calculation at the decoder helps in detecting and correcting the error bits in the data. The 3D Parity check code can correct up to 3 bits of any combination of errors in the data and the Hamming code can correct up to 3 bits in the parity, if they occur in specific combinations. Thus, this method can detect and correct errors in both data and parity bits. This method achieves higher reliability by having a slight tradeoff in area and power consumption compared to other similar methods.

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2017

Conference Paper

M. Vinodhini and Dr. N.S. Murty, “Merged arbitration and switching techniques for network on chip router”, in 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017.[Abstract]


In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput. More »»

2016

Conference Paper

N. S., S. Agrawal, and Dr. N.S. Murty, “An architecture for high speed Radix10 division”, in 2016 International Conference on Computer Communication and Informatics (ICCCI), 2016.[Abstract]


Decimal arithmetic is gaining more and more importance in business, commercial and financial applications due to error free and high speed computations. In this work, high speed radix10 divider architecture has been proposed to reduce the delay. This paper presents a modified architecture in which intermediate results are utilized to perform the high speed division. The modified architecture is simulated for different numbers of bits. Synthesis results show that the modified architecture implemented in 180nm technology has reduced delay when compared to digit recurrence with constant digit selection function architecture which is the fastest of existing architectures. More »»

2016

Conference Paper

D. Sreenivasan, Purushothaman, D., Pande, K. S., and Dr. N.S. Murty, “Dual-threshold single-ended Schmitt-Trigger based SRAM cell”, in 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 2016.[Abstract]


Data retention and power consumption during the hold mode of operation of a SRAM cell is of high importance. Hence, there is a need for a cell design that improves Static Noise Margin (SNM) and consumes low static power. This paper presents a Schmitt-Trigger (ST) based Single-Ended 11T SRAM cell that uses dual-threshold CMOS technology which exhibits high read and hold SNM and consumes low power during the hold operation. The cell is implemented in 45 nm CMOS technology using Cadence Virtuoso at supply voltage of 0.45 V. The simulation results show 89.11% decrease in the average static power dissipation of the proposed cell during the hold and read modes of operation and 38.93% decrease during write operation, when compared to that of the existing ST 11T SRAM cell for which the floating node is replaced with ground for simulation purposes. More »»

2015

Conference Paper

R. Louis, Vinodhini, M., and Dr. N.S. Murty, “Reliable router architecture with elastic buffer for NoC architecture”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


Router is the basic building block of the interconnection network. In this paper, new router architecture with elastic buffer is proposed which is reliable and also has less area and power consumption. The proposed router architecture is based on new error detection mechanisms appropriate for dynamic NoC architectures. It considers data packet error detection, correction and also routing errors. The uniqueness of the reliable router architecture is to focus on finding error sources accurately. This technique differentiates permanent and transient errors and also protects diagonal availabilities. Input and output buffers in router architectures are replaced by elastic buffers. Routers spend considerable area and power for router buffer. In this paper the proposed router architecture replaces FIFO buffers with the elastic buffers in order to reduce area, and power consumption and also to have better performance. © 2015 IEEE.

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2015

Conference Paper

Ha Kalwad, Neeharika, Sb, Divya, Sc, M. Vinodhini, and Dr. N.S. Murty, “Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


In this paper, we propose a Network on Chip router architecture with increased reliability, energy efficiency and with reduced area overhead. The proposed router architecture model adjusts dynamically to the error control strengths of the layers of NoC. In this paper, we target to optimize the combined operations of arbiter and multiplexer by using a Merged Arbiter Multiplexer (MARX) along with a dual layer cooperative error control protocol. By doing so, the number of pipe line stages, area and power consumed is reduced. We use XY Routing algorithm to send data from one router to the other when these routers are placed in network architecture. The proposed model outperforms the dual layer error control model without MARX unit. The router architecture with MARX unit has 22.7% less area and 2.4% less energy consumption than router architecture without MARX unit but has moderate increase in the delay. © 2015 IEEE.

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2015

Conference Paper

L. Vijay, Greeshma, K. K., and Dr. N.S. Murty, “Architecture for ASIC based batteryless multi-source energy harvesting system”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


This paper presents architecture of an ASIC based energy harvesting system from four sources solar, thermal, vibration and RF. A capacitor based start-up circuit is used for batteryless self-start and a supercapacitor based storage mechanism is employed for storing the harvested energy. The system includes Maximum Power Point Tracking logic based on Perturb and Observe algorithm for tracking and extracting the maximum power from solar PV source. Rectifiers and DC-DC Converters are used for extracting energy from AC sources (RF and Piezo) and thermal respectively. The system was simulated in Cadence virtuoso. Efficiencies achieved with different sources are 79.06% for Solar PV, 72.618% for Thermal, 63.84% for Piezo and 56.793% for RF. © 2015 IEEE.

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2015

Conference Paper

S. Mohan, Pande, K. S., and Dr. N.S. Murty, “Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]


Register Files (RF) are multi-port static memories with dedicated READ and WRITE ports for high bandwidth memory operations. The Register Files are important components in today's devices like Central Processing Unit (CPU) and Network Routers. Low power and area critical RF memories use SRAMs rather than the latches/flip-flops as the building block. Due to lack of performance and short channel effects, scaling of conventional MOSFETs towards Deep Submicron (DSM) dimensions in memories as well as in other System-on-Chip (SoC) designs became tedious. Recently in DSM designs, the conventional planar MOSFETs are being replaced by thin body FinFETs because of their better subthreshold swing, reduced short channel effects and better scalability. This paper proposes a 6T subthreshold 1R-2W SRAM and 8T 2R-2W SRAM bit cell designs using 25nm FinFET transistors having independent READ and WRITE ports. The proposed structures are with reduced leakage power and also show improved read stability and write stability as compared to the conventional single port SRAM structure. © 2015 IEEE.

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2015

Conference Paper

P. Sreelakshmi, Pande, K. S., and Dr. N.S. Murty, “SRAM cell with improved stability and reduced leakage current for subthreshold region of operation”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, a Modified Differential 8T SRAM cell is proposed for subthreshold region of operation. Forward Body biasing technique is used to improve the drivability of transistors and sleep transistor logic is used to reduce the leakage current in standby mode. The proposed design is implemented with 45 nm CMOS technology and is simulated using Cadence Virtuoso Simulator. At 0.5 V supply voltage, the read SNM and write SNM are 98 mV and 112 mV respectively and these are 32% and 21% higher than there reported in literature. The leakage current and power consumption of the cell are 3.26 fA and 1.63 fW respectively. © 2015 IEEE.

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2015

Conference Paper

K. T. Thoomu, Adapa, N. K., Lekkala, S. A. R., and Dr. N.S. Murty, “Comparison of Miller compensated opamps designed using planar MoS and FinFET transistors”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


Due to continuous decrease in channel length of the transistor and reduction in the supply voltages, design of operational amplifier (opamp) poses new challenges [1]. Because of the short channel effects limitations in the planar MoS technologies, alternative device structures have been developed and among those FinFET is the most prominent one. Hence, in this study we wanted to explore those advantages of FinFET over MosFET for analog IC design and hence we have designed Miller compensated opamp using 90nm MoS and 32nm FinFET devices. These were evaluated for parameters like power, voltage gain, phase margin, Gain Bandwidth Product (GBW), and slew rate. The results show that FinFET based opamp is better than MoS based opamp in many aspects, about which we have briefed in the comparison and conclusion section of the paper i.e. Section V of the paper. © 2015 IEEE.

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2015

Conference Paper

J. Jose, Pande, K. S., and Dr. N.S. Murty, “A memory architecture using linear and nonlinear feedback shift registers for data security”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, memory architecture for ensuring data security is proposed. A Graphical User Interface (GUI) is assumed in the work to enter user ID and password for each user authentication. Valid user will be given access to the corresponding data whereas invalid user will be given access but will receive garbage data to prevent multiple trails to break in. The architecture using Galois type Linear Feedback Shift Registers (LFSRs) as well as Nonlinear Feedback Shift Registers (NLFSRs) is implemented and verified for the functionality. The power consumption is estimated using 180nm Cadence RTL Compiler and the level of data security using the National Institute of Standards and Technology (NIST) test suite for random numbers and compared the results achieved through the two implementations. The power consumption is 2.291 mW for NLFSR type of implementation and is less than that of the LFSR type of implementation by 23.9%. It is observed that NLFSR type of implementation passes the four NIST tests and whereas the LFSR type of implementation fails in two out of the four NIST tests. © 2015 IEEE.

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2015

Conference Paper

J. Parimala, Priyanka, K., Kaumudi, L. S., Pande, K. S., and Dr. N.S. Murty, “Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, we present a Modified Revised Wilson Current Mirror Level Shifter (MRWCMLS) to convert subthreshold voltage to supply voltage with low leakage power. Increasing speed and complexity of today's designs resulted in increase in power consumption. System on Chip (SoC) may have few modules which are supplied with subthreshold voltage to achieve low power consumption and the remaining work with above threshold voltage supply. The level shifter which can convert subthreshold voltage level to supply voltage level is designed to minimize circuit leakage power with optimum number of transistors in the circuit. MRWCMLS has been implemented in 180 nm CMOS technology and is simulated using Cadence Virtuoso Simulator and the results are compared with the existing level shifters. In comparison with Revised Wilson Current Mirror Level Shifter (RWCMLS), the leakage power with normal transistors and with high Vth transistors type of implementation of the proposed MRWCMLS, is reduced by 34% and 43% respectively. © 2015 IEEE.

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2015

Conference Paper

L. Puneeth and Dr. N.S. Murty, “Low power clock Optimized Digital De-Skew Buffer with improved duty cycle correction”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


In this paper, we propose an architecture for Optimized Digital De-Skew Buffer (ODDB) with improved duty cycle correction using modified edge combiner and interpolator. The transmission gate based edge combiner suffers from the problem of glitches during the setup time and overshoots and undershoots afterwards. Our NAND gate based modified edge combiner, along with the interpolator, removes the glitches, drastically reduces the overshoots and undershoots and improves the duty cycle correction to deliver stable 50% duty cycle clock. A latch based clock gating circuit is used to reduce the power consumption of the ODDB. Half Delay Line blocks are used to introduce the delay and are designed using Coarse Delay Units and Fine Delay lines. The architecture is simulated using Cadence NCSim and the clock is optimized for setup time, hold time and power consumption using the Cadence SoC Encounter. The ODDB is designed and implemented using 45 nm CMOS technology with 1.1 V power supply and is optimized for 500MHz operation. The power consumption and total cell area of the ODDB are 40.6 μW and 354.312 μm2 respectively. A 6% power saving is achieved at the cost of 14% area overhead by implementing clock gating feature in ODDB. The modified edge combiner and interpolator have also been implemented using 45nm FinFET technology (BSIM CMG) and power reduction of 19% and 45% respectively are achieved when compared to the 45nm CMOS implementation. © 2015 IEEE.

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2015

Conference Paper

M. Vinodhini, Lillygrace, K., and Dr. N.S. Murty, “A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.[Abstract]


This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides crosstalk avoidance and also random and burst error correction up to 5 bits and detection up to 6 bits. The error detection outcomes at all routers in the path are recorded in the error information flit. With the help of error information flit, the error rate is calculated in the destination network interface. The calculated error rate is compared with two threshold values selected based upon the traffic pattern used. If the error rate is less than the lower threshold value, only network layer error control coding scheme is activated. If the error rate is in between the lower and higher threshold values then the error control scheme present in both network layer and datalink layer will be activated, but the error control scheme present in data link layer is activated only in the alternate routers present in the routing path. If the error rate crosses higher threshold value, error control coding scheme present in both the layers will be activated. The proposed JCA-FBEC-SBED error control coding scheme has higher reliability in terms of error detection and correction, when compared to other error control coding schemes with trade-off in delay, area and power consumption. The proposed router architecture has reduced delay and slight increase in area and power consumption of 2.1% and 5.8% respectively, when compared to the runtime adaptive scrubbing router. Our proposed fault tolerant NoC architecture theoretically provide higher data transfer reliability and energy efficiency when compared to other double layer runtime adaptive fault tolerant NoC architectures. The runtime adaptive error control reduces the overall power consumption of the NoC architecture even though JCA-FBEC-SBED decoder consumes more power compared to other schemes. © 2015 IEEE.

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