Qualification: 
Ph.D, M.E, BE
p_maran@blr.amirta.edu

Dr. P. Maran joined as Assistant Professor (Sr. Gr.) in the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru campus, on June 13, 2018. He received his Bachelors in Electronics and Communication Engineering from St. Peters Engineering College in 2011 and Masters from SSN College of Engineering in 2013. He worked as a Junior research Fellow with the department of Electronics and Communication Engineering, SSN College of Engineering towards his Ph.D.

Education

  • 2018: Ph. D.
    Anna University
  • 2013: M. E. 
    Anna University
  • 2011: B. E.
    Anna University

Publications

Publication Type: Journal Article

Year of Publication Publication Type Title

2017

Journal Article

P. Maran, Mythily Kanaga, and Premanand Venkatesh Chandramani, “Improving HRR in 3P–8P harmonic rejection mixer using modified input transconductance stage in hard switching mixer”, Analog Integr Circ Sig Process, 2017.[Abstract]


This Paper focuses on improving the Harmonic Rejection Ratio (HRR) and the linearity of 3-Path 8-Phase harmonic rejection mixer with modified transconductance stage. The mixer core incorporates a feed-forward compensation technique in the transconductance stage for improving the linearity of the mixer with an Third order Input Intercept Point (IIP3) of 14 dBm. The Harmonic Rejection Mixer (HRM) using mixer cores with modified transconductance stage was designed using 90 nm CMOS process technology and the simulation results shows an improvement of IIP3 point of more than 25 dBm. A conversion gain of 12–4 dB was observed over the frequency range of 2.26–2.8 GHz (540 MHz bandwidth). Maximum third order HRR (HRR3) of 45 dB and fifth order HRR (HRR5) of 55 dB was observed on sweeping the RF power from -30 to 10 dBm. Deviations on the performance of the HRM was found to be very minimal on PVT variation. More »»

2016

Journal Article

P. Maran, N. Vinodhkumar, R. Srinivasan, and Premanand Venkatesh Chandramani, “Phase displacement study in MOSFET based ring VCOs due to heavy-ion irradiation using 3D-TCAD and circuit simulation”, Microelectronics Reliability, vol. 65, pp. 27 - 34, 2016.[Abstract]


This paper analyzes the radiation tolerance of both single ended and differential ring VCO in the presence of SET in 90nm CMOS process technology. Phase displacement is an important metric in assessing the susceptibility and suitability of any frequency synthesizer in the presence of SET. Through device level characterization using Synopsys TCAD and extensive circuit level simulation and verification, for heavy ion dosage with LET between 20 ((MeV-cm2)/mg) and 200 ((MeV-cm2)/mg), the current starved differential delay cell based 3-stage differential ring VCO exhibits a phase displacement improvement of around 20% compared to a current starved inverter based single ended ring VCO oscillating at 420MHz. When the number of stages in differential ring VCO are increased from 3 to 7 the phase displacement is reduced by a factor of 57%. However, to achieve similar phase displacement improvement in inverter based single ended ring VCO required in excess of 15 stages. The active area for the differential ring VCO decreases by almost 40% as the number of stages increases. More »»

Publication Type: Conference Paper

Year of Publication Publication Type Title

2016

Conference Paper

A. J Twinkle, P. Maran, and Premanand Venkatesh Chandramani, “Single Event Upset In a 3-Bit SAR ADC”, in National Conference on Research Challenges in VLSI Design and embedded Systems for Wireless Communication, 2016.

2016

Conference Paper

P. Maran and Premanand Venkatesh Chandramani, “SET induced Soft-error study of two stage ADC with VCO based ADC on the second stage”, in National Conference on Reliability and Safety Engineering, NCRS 2016. , 2016.

2014

Conference Paper

A. Padmanaban M., P. Maran, and Premanand Venkatesh Chandramani, “Design and implementation of two stage 5-bit pipelined SAR ADC”, in 2014 International Conference on Communication and Signal Processing, 2014.[Abstract]


A 250 MS/s cascaded two-stage 5-bit pipelined SAR ADC in 90nm CMOS was designed and validated. Elimination of passive components leads to an improvement in power utilization, improvement in speed and at the same time is not limited by process variations. The SAR ADC design was validated as a Matlab/Simulink macro model and verified in 90nm CMOS through Agilent ADS. Successive approximation for each stage is achieved through a binary search in a round robin mode that reduces the approximation time. DNL was observed to be 0.7 LSB.

More »»

2014

Conference Paper

T. V, P. Maran, and Premanand Venkatesh Chandramani, “Spur reduction technique for fractional-N frequency synthesizer with MASH 1-1-1-1 Sigma Delta modulator”, in 2014 International Conference on Communication and Signal Processing, 2014.[Abstract]


A fourth order MASH Sigma Delta modulator based fractional-N frequency synthesizer was designed and validated as a Matlab/Simulink macro- model. Use of MASH achieves a better noise shaping for the frequencies generated by the synthesizer. With a reference frequency of 20MHz, the fractional-N frequency synthesizer achieves a synthesized frequency range of 200MHz to 220MHz with 2 MHz resolution. The macro-model has a gain margin of 6.02dB and a phase margin of 39.7°, ensuring the stability of the closed loop system with settling time of 3.32μ sec. Spurs that were introduced by the fractional feedback and reference input are removed through notch type Comb filter.

More »»

2013

Conference Paper

P. Maran and Premanand Venkatesh Chandramani, “Injection locked differential ring VCO”, in 2013 IEEE Conference on Information Communication Technologies, 2013.[Abstract]


This paper proposes an injection locked four stage differential ring voltage controlled oscillator (VCO), in which in-phase and quadrature phase of the reference signal is injected after the first stage, for both frequency multiplication and division. The free running frequency of 4-stage differential VCO is 485MHz. Frequency Multiplication is carried out by injecting a reference frequency of 1.25GHz the corresponding output frequency observed is 1.25GHz. Frequency division is carried out by injecting a reference frequency of 242MHz and a corresponding output frequency of 250MHz is observed.

More »»

2012

Conference Paper

P. Maran, Madhankumar, E., and Mathivanan, P., “Design of Control Circuit for Torsion Bar Testing Machine”, in International Conference & Workshop on Recent Trends in Technology, 2012.[Abstract]


In today’s industrial and research laboratories more applications are calling for control and data acquisition (DAQ) devices. Personal computers have become a primary tool in data acquisition with the development of hardware and software interfaces. Our paper is aimed at developing a control circuit for the torsion bar testing machine. The torsion bar testing machine is used to increase the resilience of the torsion bar i.e. to increase the elasticity of the torsion bar and as well as to check the quality of the manufactured bar. The existing circuit for the torsion tester is designed to be compatible with the ISA bus of the main computer but in today’s modern world ISA bus has become obsolete with the introduction of the more efficient PCI bus and our project is aimed at designing a control circuit that is compatible with the PCI bus of the main system and also to reduce the circuit complexity. The main advantages of the PCI bus over ISA are high bandwidth and speed and no address conflict problems which helps in efficient operation of the machine. One part of the project involves in making PCI I/O card that is concerned with passing the control signal to the rotor and as well passing angular position of the rotor to the main system and the second part of project involves in designing the circuit that controls the rotor of the machine.

More »»
Faculty Research Interest: 
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