Qualification: 
Ph.D, M.E, BE
purushothamana@am.amrita.edu
Phone: 
+918086035865

Dr. Purushothaman A. currently serves as Associate Professor and Vice Chairperson at the Department of Electronics and Communication Engineering at Amrita School of Engineering, Amritapuri. He is completed his B.E. in Electrical and Electronics Engineering from MS University, India in 2002. He pursued an M. Tech. in Applied Electronics from Anna University and received his Ph.D. in Information and Communication Technology from Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar in November 2012. 

His research interests include Nyquist ADC and low-power integrated circuits design. Currently, his research mainly focuses on SA and Pipeline algorithms and design of ultra low-power ADC.

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2018

Conference Paper

D. James, Abhishek, K., Dr. Purushothaman A., and Sahoo, B., “Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplifier”, in 31st International conference on VLSI Design, 2018.

2016

Conference Paper

Dr. Purushothaman A., “MINLP Based Power Optimization for Pipelined ADC”, in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, vol. 2016-September, pp. 508-511.[Abstract]


This paper proposes a Mixed Integer Non-linear Programming (MINLP) based optimization algorithm to design power optimized pipelined ADC. For a given specification the proposed algorithm gives stage resolution and sampling capacitor per stage that minimizes the total power consumption. Closed form expressions of the power consumption of each stage were derived and used as objective function. Pipelined ADCs of various specifications, viz., 10-bit, 12-bit, and 16-bit, were designed and validated using this algorithm. More »»

2016

Conference Paper

Dr. Purushothaman A., “Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method”, in 20th International Symposium on VLSI Design and Test (VDAT), Guwahati, India, 2016.[Abstract]


This paper presents Adomian Decomposition based analysis of regeneration time constant of CMOS dynamic cross-coupled latch. A CMOS dynamic cross-coupled latch, which is a nonlinear system, is typically analyzed by linearizing it around an operating point to arrive at regeneration time constant. However, the time domain behavior obtained using the linear analysis deviates from the actual behavior of the latch. Thus, circuit simulators like SPICE and Spectre solve the nonlinear differential equations numerically to obtain the time domain behavior. These numerical solutions neither give a closed form expression of the regeneration time-constant nor do they give an expression of time domain behavior in closed form. Adomian Decomposition Method (ADM), however, can be used to obtain the complete time-domain behavior and the regeneration time-constant. ADM expresses the solution of a nonlinear differential equation in a manner similar to Taylor series approximation of a polynomial. The paper first introduces the concept of ADM and then applies it to RC linear circuits. c. Simulations show good agreement between Cadence based and ADM based time domain behavior.

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2011

Conference Paper

Dr. Purushothaman A. and Parikh, C. D., “Automating the design of Successive Approximation Register Analog to Digital Converters”, in 11th International Symposium on VLSI Design and Test, 2011.

2010

Conference Paper

Dr. Purushothaman A. and Parikh, C. D., “Design of static latch based comparator using power constrained optimization”, in 10th International Symposium on VLSI Design and Test, 2010.

2008

Conference Paper

Dr. Purushothaman A. and Kumar, C. V. Vijaya, “Implementation of bit level Super systolic RLS adaptive filter using FPGA”, in 10th International Conference on Radio Science (ICRS), 2008.

Publication Type: Journal Article

Year of Publication Publication Type Title

2017

Journal Article

Rajeswari P., Shekar G., Devi S., and Dr. Purushothaman A., “Geometric Programming-Based Power Optimization and Design Automation for a Digitally Controlled Pulse Width Modulator”, Circuits, Systems, and Signal Processing, 2017.[Abstract]


This paper proposes a tool for the synthesis of the design and optimization of digitally controlled pulse width modulator (PWM). There are three phases for the proposed tool. In the first phase, an accurate transistor level model for 90 nm fabrication technology is generated using MATLAB curve-fitting tool box (Dunbar in Am J Phys 24(6):464–464, 1956) and Cadence Spectre Circuit Simulator, which successfully replicates the transistor performance of Cadence 90 nm fabrication technology. In the second phase, the PWM specification is optimally decomposed among its subcomponents. The optimized design of subcomponents is accomplished via Geometric programming in the third phase. A practical design example in Cadence 90 nm fabrication technology is presented to substantiate the suggested methodology for unified design automation and power optimization.

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2015

Journal Article

Dr. Purushothaman A. and Parikh, C. D., “A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators”, Circuits, systems and Signal processing, Springer, vol. 34, pp. 2749-2764, 2015.[Abstract]


Comparators are the main components in several analog and mixed-signal systems. Design and synthesis of comparator architectures largely remain an analog designer’s art. In this work, we present a systematic methodology for designing comparators using the method of constrained optimization. Constrained optimization is an equation-based optimization method and requires accurate equations. We propose a new delay equation for latch-based comparators. The new delay model is based on Adomian decomposition method and gives more accurate delay characteristics compared with the conventional one. The architecture is optimized for total power dissipation with speed, area and noise as the constraints. Geometric programming-based automation algorithm and the behavioral model of the comparator architecture are written in MATLAB. The optimized schematic is drawn in Cadence 180 nm technology, and the results are verified with MATLAB. © 2015, Springer Science+Business Media New York.

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2015

Journal Article

Dr. Purushothaman A. and Parikh, C. D., “A low power low area capacitor array based Digital to Analog Converter architecture”, Microelectronics Journal, vol. 46, no. 10, pp. 928–934, 2015.[Abstract]


This paper presents a capacitor based Digital to Analog Converter architecture, which gives comparable performance with the conventional architecture with approximately half the total capacitance. The proposed architecture reduces the area and power dissipation in comparison with the conventional scheme. Further to these advantages, the proposed DAC architecture does not demand an additional reference voltage or an additional switching circuit. Closed form formulas to estimate the standard deviation of INL, DNL and the power consumption are derived. A comparison is also made between the standard architectures and the proposed architecture for the same unit capacitor, in addition to analyzing the capacitor parasitics and mismatches. These analytical comparisons are validated by simulating the proposed architecture and all the other conventional architectures for 10 bits with UMC 180 nm CMOS technology.

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