Resmi R. currently serves as Assistant Professor (SR) at Department of Electrical and Electronics Engineering, School of Engineering, Coimbatore Campus. Her areas of research include Control Systems.


Publication Type: Conference Paper

Year of Publication Title


J. Srinivasan, Selvaraj, K., Chitrarasu, J., and Resmi, R., “Design and analysis of squirrel cage induction motor in short pitch and full pitch winding configurations using FEA”, in Proceedings of IEEE International Conference on Emerging Technological Trends in Computing, Communications and Electrical Engineering, ICETT 2016, 2017.[Abstract]

Squirrel cage induction motors are very popular in industrial and manufacturing process because of its reliability, low cost and rugged construction. In this paper, three phase, 1.1 kW, 500 rpm Squirrel Cage Induction Motor is designed for 12 pole configuration. The performance of the motor due to full pitch and short pitch winding configurations are analysed and the results obtained are compared. Finite element method is used for the analysis and verification. In addition to that, the harmonics of winding current of the motor is compared for both configurations. The analysis is performed using ANSYS MAXWELL software which is a powerful tool to analyse the performance of machines. © 2016 IEEE. More »»


P. Sahin, Resmi, R., and Dr. Vanitha V., “PMSG based standalone wind electric conversion system with MPPT”, in Proceedings of IEEE International Conference on Emerging Technological Trends in Computing, Communications and Electrical Engineering, ICETT 2016, 2017.[Abstract]

Today wind energy has emerged as an alternative energy source for power generation. This paper investigates about standalone Permanent Magnet Synchronous Generator (PMSG) based wind energy conversion system (WECS) with Maximum Power Point Tracking (MPPT). The proposed system comprises of Wind turbine (WT), PMSG, boost converter, uncontrolled diode rectifier, battery bank, bidirectional buck boost converter and dc load. Multi pole PMSG is best suited for low speed, wide range variable speed wind energy applications. Wind flow varies with time; as a result power produced also varies. As maximum power has to be tracked for varying wind speeds, perturbation & Observation (P&O) algorithm is implemented for MPPT. Battery storage system is essential to supply the load during low wind speed condition. In this paper, a simulation study of the proposed standalone system is done using SIMULINK in MATLAB. © 2016 IEEE. More »»

Publication Type: Journal Article

Year of Publication Title


L. Devadas, Vanitha, V., and Resmi, R., “Modified Double Vector Control Theory Based Dynamic Voltage Restorer”, International Journal of Applied Engineering Research, vol. 10, 2015.

Publication Type: Conference Proceedings

Year of Publication Title


R. Resmi and Dr. Bala Tripura Sundari B., “Allocation of Optimal Reconfigurable Array using Graph Merging Technique”, International Conference on Embedded Systems (ICES), 2014 . Coimbatore; India, pp. 49-54, 2014.[Abstract]

Inherent parallelism in the nested loop algorithms can be exploited by proposing an array architecture called systolic array and mapping the computational tasks of the algorithm using a suitable mapping methodology on to the array architecture. The computational subspace mapping methodology that identifies a lower dimension subspace of a higher dimensional problem is implemented using the technique of allocation. i.e., the lower dimensional sub-space is chosen to lie along the computational equation. The best computational direction for higher dimensional problem in terms of data reuse, number of ports, number of PEs, memory read is selected by multi-objective functions. A reconfigurable array for n-D nested loop problems is designed by graph merging approach which reduces the area and power compared with reconfigurable array using multiplexers. The algorithms under consideration here are the 3-D matrix-matrix multiplication, 2-D spatial filtering algorithm which is a 4-D nested loop algorithm and 6-D full search block motion estimation. Allocation and scheduling of reconfigurable array is implemented in Verilog HDL and synthesized by RTL behavioral representation using Xilinx ISE Design Suite 12.1. The graph merging approach is validated by the results which show that the area allocated is less for graph merging technique than the reconfigurable array using multiplexers.
Article number 6953049, Pages 49-54, 3 July 2014 through 5 July 2014, Category numberCFP1440Y-ART, Code 109145

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