Qualification: 
Ph.D, M.E, BE
Email: 
rameshb@am.amrita.edu

Dr. Ramesh Bhakthavatchalu received his B.E from Vellore Institute of Technology in April, 1994. He completed his M.E in Applied Electronics from College of Engineering, Anna University, Chennai in the year 1998.

He served as Senior Design Application Engineer in Cirrus Logic Inc., USA and Syntest Technologies, USA for 8 years. He has taped out 4 designs during his tenure in VLSI Industry.

Currently he is working as Assistant professor in ECE department of Amrita Vishwa Vidyapeetham, Amritapuri, India. His areas of expertise are Design For Testability, FPGA based system design, VLSI signal processing. He has published more than 15 international conference and journal papers in VLSI design and testing area in last 3 years.

He has given invited talks at various national workshops and seminars in India. He received the Award of Excellence from Amrita Vishwa Vidyapeetham, for excellent performance during the academic year 2010-2011. He has more than 15 years of experience combined in VLSI industry in USA and teaching experience in India.

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2016

Conference Paper

M. K. Dinesh and Dr. Ramesh Bhakthavatchalu, “Storage memory/NVM based executable memory interface IP for advanced IoT applications”, in 2016 International Conference on Recent Trends in Information Technology, ICRTIT 2016, 2016.[Abstract]


Internet of Things (IoT) devices is getting increasingly popular in every aspect of life. From health care monitors, activity/sleep trackers to industry/home automation, IoT devices and system-on-chip (SoC) have huge research potential. This paper presents a new memory interface intellectual property (IP) developed for interfacing IoT SoC with storage class memory or non-volatile memory (NVM). So the novelty of this IP is that it enables storage class memory which stands invisible to core as executable memory for low to medium sized IoT SoC's. Currently the devices available in the market have to be synced in to cloud or a device with higher memory bandwidth frequently as the inbuilt SRAM/DDR memory have limited executable memory space. So this interface can be used in the SoC with a high capacity NVM using an interface IP using advanced caching algorithms, this potential limitation can be eliminated. © 2016 IEEE. More »»

2016

Conference Paper

J. Kumar, Kumar, J., Murali, S., and Dr. Ramesh Bhakthavatchalu, “Design and implementation of Izhikevich, Hodgkin and Huxley spiking neuron models and their comparison”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 111-116.[Abstract]


The elementary processing units in brain are neurons which are connected to each other in many shapes and sizes. A typical neuron can be divided into functionally three distinct parts called Dendrites, Soma and Axon. Dendrites play the role of input device that collect signals from other neurons and transmits them to soma. Soma performs a Non-linear operation, i.e. if input exceeds a certain threshold, an output signal is generated. This output signal is taken over by an output device, the Axon, which delivers the signal to other neurons. This is the basic function of a biological neuron. A biological neuron model which is also known as Spiking Neuron Model is a mathematical description of properties of neuron that is to be designed accurately to describe and predict the biological processes. So there comes the concept of modelling and analysis of neurons. Modelling and analysis of neurons was performed by different researchers on First, Second and Third generation of neurons. The Third generation of neurons are also called as spiking neurons. The focus of this work is to implement different types of spiking neuron models developed by Izhikevich which is a mathematical model and Hodgkin and Huxley which is a biological model. Comparison between these two models in terms of Design implementation has been done. These both model simulations are done in MATLAB and they are modelled using digital logic circuits in Verilog Hardware Description Language (HDL) and simulated in ModelSIM RTL simulator. These models are then implemented in Xilinx FPGA and checked for the functionality. © 2016 IEEE.

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2016

Conference Paper

Dr. Ramesh Bhakthavatchalu, Rekha, B. S., Divya, G. A., and Jyothi, V. U. S., “Design of AXI bus interface modules on FPGA”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 141-146.[Abstract]


This paper describes the design and implementation of programmable AXI bus Interface modules in Verilog Hardware Description Language (HDL) and implementation in Xilinx Spartan 3E FPGA. All the interface modules are reconfigurable with the data size, burst type, number of transfers in a burst. Multiple masters can communicate with different slave memory locations concurrently. An arbiter controls the burst grant to different bus masters based on Round Robin algorithm. Separate decoder modules are implemented for write address channel, write data channel, write response channel, read address channel, read data channel. The design can support a maximum of 16 masters. All the RTL simulations are performed using Modelsim RTL Simulator. Each independent module is synthesized in XC3S250EPQ208-5 FPGA and the maximum speed is found to be 298.958 MHz. All the design modules can be integrated to create a soft IP for the AXI BUS system. © 2016 IEEE.

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2014

Conference Paper

Dr. Ramesh Bhakthavatchalu, Krishnan, S., Vineeth, V., and Dr. Nirmala Devi M., “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.[Abstract]


A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented. This technique uses an offline algorithm to search and classify the random patterns based on the deterministic test patterns generated by the automatic test pattern generator (ATPG). The seed activated linear feedback shift register (LFSR) generates exhaustive test patterns which are applied on any design under test (DUT). The responses are received at the output of the scan chains in the DUT and they are compressed to produce a signature. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns than an arbitrary seed. Also, this technique helps to estimate the number of BIST test patterns to be generated to achieve specific fault coverage. Results on six ISCAS-89 designs with the help of Cadence Encounter true time 13.1 ATPG is shown. © 2014 IEEE.

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2013

Conference Paper

Dr. Ramesh Bhakthavatchalu, Kripalal, A., Nair, S., Venugopal, P., and Viswanath, M., “Modified FPGA based design and implementation of reconfigurable FFT architecture”, in Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013, Kerala, 2013, pp. 818-822.[Abstract]


Fast Fourier Transforms, popularly known as FFTs, have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily Area, Memory and Speed. The aim is to build a Reconfigurable Fast Fourier Transform Block which is suitable for any signal processing application, especially for communication blocks such as OFDM receivers. The objective is to design an FFT block that is capable of computing any N-point FFT and employs R2SDF (Radix 2 Single Delay Feedback) architecture with a single ROM. The design has been developed using the hardware description language VHDL on Xilinx xc5vlx110t. The result shows significant reduction in area for this architecture. © 2013 IEEE.

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2013

Conference Paper

Dr. Ramesh Bhakthavatchalu, Karthika, V. S., Ramesh, L., and Aamani, B., “Design of optimized CIC decimator and interpolator in FPGA”, in Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013, Kerala, 2013, pp. 812-817.[Abstract]


Cascaded Integrator Comb (CIC) filters are extensively used in Multirate signal processing as a filter for both decimation and interpolation processes. This paper analyzes optimized architecture and implementation aspects of decimator and interpolator using CIC filter and comparison between the results in hardware and simulations. The hardware is synthesized in FPGA and verified with Modelsim and Matlab simulation results. CIC filters function as efficient anti-aliasing filters before downsampling of signals in decimation process and as anti-imaging filters after upsampling of signals in interpolation process. This paper also discusses about pipelining, throughput and area reduction techniques and performance analysis with respect to the number of stages (N) and rate change factor (R) of the filter. © 2013 IEEE.

More »»

2011

Conference Paper

Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Vidhya, S., and Nisha, V., “Analysis of low power open core protocol bridge interface using VHDL”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 357-362.[Abstract]


System on Chip (SoC) design is becoming challenging due to its complexity and the necessity of Intellectual Properties (IP) reuse to shorten the design time. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. I2C is a simple bi-directional two wire bus for efficient inter IC control. This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. The power reduction using Multi voltage design is the important feature of the paper. The developed FSM's for OCP and I2C were implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1 and Synopsys ASIC synthesis tool design compiler. More »»

2011

Conference Paper

Dr. Ramesh Bhakthavatchalu, N Kareem, A., and Arya, J., “Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 343-347.[Abstract]


In this work, two different methodologies for the implementation of a Fast Fourier transform processor: FFT using CORDIC and FFT using Multiplier are investigated. Reconfigurable FFT using radix-2 Decimation in frequency technique is chosen for the comparison. In terms of area and power, both the implementations were analyzed. Coordinate Rotation Digital Computer (CORDIC) is widely used in DSP applications. It utilizes only add and shift operations instead of multipliers. Both CORDIC and multiplier are employed here for twiddle factor multiplication. The experimental result shows that the multiplier based FFT implementation has lower area and power consumption, as compared to CORDIC based implementation. More »»

2011

Conference Paper

Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Mallia, S. S., HariKrishnan, R., Krishnan, A., and Sruthi, B., “32-bit reconfigurable logic-BIST design using Verilog for ASIC chips”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 386-390.[Abstract]


The BIST technique for logic circuits improves access to internal signals from primary input/outputs. This paper presents programmable logic BIST architecture for testing ASIC chips. The scheme is based on STUMPS [6] (Self Test Using MISR [4, 6] and Parallel Shift register) architecture which uses an on-chip circuitry to generate the test patterns and analyze the responses with no or little help from an ATE. External operations are required only to initialize the Built-in tests and to check the test results. The system is synthesized in Xilinx ISE 10.1 to get the frequency of operation and in Design Compiler for timing Analysis. Multi Voltage design for power reduction is successfully implemented. More »»

2011

Conference Paper

Dr. Ramesh Bhakthavatchalu and Prem, N., “Low power design techniques applied to pipelined parallel and iterative CORDIC design”, in ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, vol. 5, pp. 336-340.[Abstract]


CORDIC (COrdinate Rotation for Digital Computers) is a hardware efficient algorithm that can be used for the implementation of all kinds of digital signal processing architectures used in most of the processing instruments. Today, for most electronic designs, power budget is one of the most important design goals. The paper analyses clock-gating technique, a simple method for power reduction, applied to the different CORDIC architectures and compares their performance especially in three different major styles iterative, parallel and pipelined structures. The core is designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. © 2011 IEEE.

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2011

Conference Paper

Dr. Ramesh Bhakthavatchalu, S. Mallia, S., Harikrishnan, R., Krishnan, A., and Sruthi, B., “Low power scheduled alarm system using embedded microcontroller with USB interface”, in 2011 International Conference on Emerging Trends in Electrical and Computer Technology, ICETECT 2011, Chunkankadai, 2011, pp. 610-615.[Abstract]


This paper discusses about the design and implementation of low power automatic scheduled alarm system whose schedule and time can be programmed using a computer via Universal Serial Bus port. Educational institutions, Factories, hospitals, etc are some places where this can be primarily used. The system uses an 8 bit PIC18f4550 microcontroller, a DS12626 Sanyo 16x2 character LCD, a DS1208 Real Time Clock (RTC) and an electrical relay to drive the ringer. The LCD displays the calendar details like day, date, time with second's accuracy. Stress is given on low power consumption system design. Power savings compared to 7segment display is also discussed. Power consumption is lowered by using ultra low power techniques by disabling unused peripheral units and by introducing sleep mode. The power down mode of the system does not affect alarm system or the display system. This is one of the advantages. The design is initially verified using MPLAB IDE and Proteus lite simulator and then the real hardware is implemented. Complete power analysis with specific interfaces of the system is also performed. © 2011 IEEE. More »»

2011

Conference Paper

Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Vidhya, S., and Nisha, V., “Design and analysis of low power open core protocol compliant interface using VHDL”, in 2011 International Conference on Emerging Trends in Electrical and Computer Technology, ICETECT 2011, Chunkankadai, 2011, pp. 621-625.[Abstract]


The necessity of Intellectual Properties (IP) reuse to shorten the design time and the complexity makes the large scale System On Chip (SoC) more challenging. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. I2C is a simple bi-directional 2-wire bus for efficient inter-IC control. The developed FSM's for OCP and I2C were implemented using VHDL and the synthesis is done using Xilinx ISE 10.1. © 2011 IEEE. More »»

2010

Conference Paper

Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., and Shanooja, S., “Implementation of re-configurable open core protocol compliant memory system using VHDL”, in 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Mangalore, Karnataka, 2010, pp. 213-218.[Abstract]


The design of a large scale System on Chip (SoC) is becoming challenging not only due to the complexity but also due to the use of a large amount of Intellectual Properties (IP). An interface standard for IP cores is becoming important for a successful SoC design. In a SoC the different IP cores are interfaced through different protocols. It increases the complexity of the design. Open Core Protocol (OCP) is an openly licensed core centric protocol intended to meet contemporary system level integration challenges. OCP promotes IP core reusability and reduces design time, design risk and manufacturing costs for SoC designs. OCP defines a highly configurable interface including data flow, control, verification and test signals required to describe an IP core's communication. This paper focuses on the design and implementation of a reconfigurable OCP compliant master slave interface for a memory system with burst support. An OCP compliant memory system was designed and shown that the use of OCP wrapper reduces the power and increases the speed of the system. The proposed design was implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1.Experimental results are included. ©2010 IEEE. More »»

2010

Conference Paper

Dr. Ramesh Bhakthavatchalu, Sinith, M. S., Prem, N., and Jismi, K., “A comparison of pipelined parallel and iterative CORDIC design on FPGA”, in 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Mangalore, Karnataka, 2010, pp. 239-243.[Abstract]


Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (COrdinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. The paper compares the different CORDIC architectures with respect to their area, speed, and data throughput performance especially in three different major styles iterative, parallel and pipelined structures. All three designs were designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. ©2010 IEEE.

More »»

Publication Type: Journal Article

Year of Publication Publication Type Title

2015

Journal Article

Dr. Ramesh Bhakthavatchalu and Dr. Nirmala Devi M., “Deterministic seed selection and pattern reduction in logic BIST”, International Journal of Applied Engineering Research, vol. 10, pp. 7537-7551, 2015.[Abstract]


<p>A technique to select the proper seed and to reduce the number of test patterns generated in Logic Built in Self Test (BIST) is proposed. This paper explains the algorithm that can be used offline of BIST flow to search and classify the random patterns based on the deterministic test patterns generated by the Automatic Test Pattern Generator (ATPG). The seed activated Linear Feedback Shift Register (LFSR) generates exhaustive test patterns which are applied on any Circuit Under Test (CUT). The responses are received at the output of the scan chains in the CUT and they are compressed to produce a signature. This signature is compared with the expected golden signature to indicate the BIST status. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns compared to an arbitrary seed. This technique is well suited for any scan based sequential design. It is applied on ISCAS-89 designs with the help of Cadence Encounter Test Architect 13.1 tool. The results show that this method is comparable with similar methods. Possible limitations of this technique when employed in large designs and solutions are also suggested as future work. © Research India Publications.</p>

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2015

Journal Article

Dr. Ramesh Bhakthavatchalu, Kannan, S. K., and Dr. Nirmala Devi M., “Verilog design of programmable JTAG controller for digital VLSI IC's”, Indian Journal of Science and Technology, vol. 8, 2015.[Abstract]


The objective of this work is to design and implement a custom reconfigurable JTAG controller in Verilog. It can be directly inserted in to a new digital IC designs with little modifications. It is fully compatible with IEEE 1149.1 standards. Additional programmable private instructions can also be added in to the design. A secure access mechanism is provided in to the controller which helps in protecting the system by preventing the un-authorized users from interfering with the system functions. A locking and opening mechanism and a password key based access control were incorporated as part of the JTAG controller module. The controller was configured to fit into different ISCAS'89 digital VLSI benchmark designs and results are analysed. It is observed that as the design size increases the area and power overhead decreases but the number of boundary scan vectors increases. All the designs were written in Verilog and RTL simulations were performed using Cadence NC-Sim Simulator. Cadence Encounter Test Architect 13.1 was used to check the boundary scan flow and analysis. A line graph to depict the power and area overhead is also shown. Complete performance analysis of the ISCAS'89 designs with and without the JTAG controller was performed. The power and area overhead was found to be negligible as the size of the VLSI designs increases.

More »»

2015

Journal Article

Dr. Ramesh Bhakthavatchalu and Dr. Nirmala Devi M., “Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture”, International Journal of Engineering and Technology, vol. 7, no. 3, pp. 973-984, 2015.[Abstract]


A technique to provide programmable secure access to the scan based Logic Built in Self- Test (BIST) structures is proposed. Joint Test Access Group (JTAG) interface is the major test access method used in VLSI IC’s. At the same time, it can be misused as a means to access and hack the hardware circuitry of the IC. It is addressed in this method to prevent unauthorized users from hacking the JTAG interface and interfering in the Logic BIST test functions. A two stage, multiple crypto algorithms based separate authorization schemes are used. A configuration register can be programmed to select the level of security to a specific user group. Different crypto algorithms can be chosen, with user specifiable key lengths. A challenge response protocol is employed to authenticate the user and corresponding accessibility. All the features included are compliant with the IEEE JTAG standard 1149.1. This technique is applied on ISCAS-89 and ISCAS-99 benchmark designs with the help of Cadence Encounter true time 13.1 design automation tools and results are shown. A small amount of (less than 2 to 5%) increase in area reported for implementing the security features.

More »»

2011

Journal Article

Dr. Ramesh Bhakthavatchalu, Karthika, V. S., and Ramesh, L., “Design and Implementation of Improved Attenuation CIC Decimator and Interpolator in FPGA”, Int. J. on Recent Trends in Engineering and Technology, vol. 6, pp. 18-22, 2011.[Abstract]


Cascaded Integrator Comb (CIC) filters are widely used in Multirate signal processing as a filter in both decimator (decrease in the sampling rate) and interpolator (increase in the sampling rate). This paper discusses the architecture, design and implementation aspects of decimator and interpolator using CIC filter and comparison between the results in hardware and simulations. The hardware is implemented in FPGA and verified with Modelsim & Lab VIEW simulation results. CIC filters serve as powerful anti aliasing agents before decimation and anti- imaging agents for interpolated signals. This paper also discusses about the method to improve the CIC attenuation. CIC Decimator and Interpolator were coded in Verilog, simulated using Modelsim simulator and Lab VIEW and implemented using Xilinx FPGA device. More »»

2011

Journal Article

Dr. Ramesh Bhakthavatchalu, Bhadran, B. R. K., and M Hari, A., “Analysis of Fixed Width and Flexible Width TBA and TRA Test Architectures for Soc Design”, International Journal on Recent Trends in Engineering & Technology, vol. 6, no. 2, pp. 200-203, 2011.[Abstract]


System-on-Chip (SoC) design refers to integrating all components of a computer or other electronic system in to a single integrated circuit. Testing of System-on-chip (SoC) design is becoming a challenging job due to its inherent complexities and higher chip densities. We present a new testing technique to reduce the number of test pins available for test and hence to reduce the test cost. The paper introduces the concept of flexible width test architectures instead of fixed width test architectures. The paper analyzes fixed width and flexible width Test Bus Architecture (TBA) and Test Rail Architecture (TRA) possible for a sample SoC designs. Test strategy for all designs coded in Verilog or VHDL is implemented using Synopsys DFT Compiler and ATPG is run through Synopsys TetraMAX ATPG tool. More »»

2011

Journal Article

Dr. Ramesh Bhakthavatchalu, “Analysis of Low Power Open Core Protocol Complaint Memory Interface Using VHDL”, Procedia Engineering, 2011.

2011

Journal Article

R. Harikrishnan, Krishnan, A., S. Mallia, S., Sruthi, B., and Dr. Ramesh Bhakthavatchalu, “A Mobile Phone Controlled Remote Robot”, Procedia Engineering, 2011.

2011

Journal Article

S. S. Mallia, Harikrishnan, R., Krishnan, A., Sruthi, B., and Dr. Ramesh Bhakthavatchalu, “A Design and implementation of an intelligent performance optimized low power scheduled alarm system using Embedded Microcontroller”, Procedia Engineering, 2011.

2010

Journal Article

K. Aditya, Dinesh, P., and Dr. Ramesh Bhakthavatchalu, “Reconfigurable autonomous mini robot design using CPLD's”, World Academy of Science, Engineering and Technology, vol. 65, pp. 785-789, 2010.[Abstract]


This paper explains a project based learning method where autonomous mini-robots are developed for research, education and entertainment purposes. In case of remote systems wireless sensors are developed in critical areas, which would collect data at specific time intervals, send the data to the central wireless node based on certain preferred information would make decisions to turn on or off a switch or control unit. Such information transfers hardly sums up to a few bytes and hence low data rates would suffice for such implementations. As a robot is a multidisciplinary platform, the interfacing issues involved are discussed in this paper. The paper is mainly focused on power supply, grounding and decoupling issues. More »»

Publication Type: Conference Proceedings

Year of Publication Publication Type Title

2014

Conference Proceedings

Dr. Ramesh Bhakthavatchalu, Dr. Nirmala Devi M., and Krishnan, S., “Reconfigurable Logic Built in Self-Test technique for SoC Applications”, International Conference on Communication and Computing, ICC 2014, vol. 3. Elsevier, Bangalore, India, pp. 16-23, 2014.

 

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