Qualification: 
MS, B-Tech
s_geethu@cb.amrita.edu

Geethu S. currently serves as an Assistant Professor at the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore campus.

Geethu received her B. Tech. degree in Electronics and Communication Engineering from CUSAT in 2010, and the MS degree in VLSI from National Institute of Technology, Tiruchirappalli, Tamil Nadu, India, in 2014. She submitted her Ph. D. thesis on “High-Performance VLSI Architectures for Polar Decoder and Interleaver” to the National Institute of Technology Tiruchirappalli, Tamil Nadu, India.

Her research interests include VLSI Architecture for Multistandard Wireless Communication Systems, Cognitive Radio, Polar Codes, etc. She was endorsed to visit Heriot-Watt University, Edinburgh, through a student exchange program sponsored by UKIERI. She received the best presentation award at the IEEE InternationalConference on Emerging Trends in Computing, Communication, and Nanotechnology. She has published research papers in refereed international journals and conferences.

Education

  • 2019 (Thesis Submitted): Ph. D. (Digital VLSI Design)
    National Institute of Technology, Tiruchirappalli
  • 2014: MS (By research) VLSI Systems
    National Institute of Technology Tiruchirappalli 
    Qualified GATE – 2011 (MTech Fellowship)

Professional Appointments

Year Affiliation
July 1, 2019 - Present Assistant Professor, Amrita Vishwa Vidyapeetham
Domain: Teaching and Labs
September 9, 2013 - November 18, 2013 Assistant Professor, Sastra University, Tanjavur
Domain: Teaching and Labs

Academic Responsibilities

  • 2019 – 2023 (CCE): Class Advisor

Courses Handled (Undergraduate)

  • Linear Integrated Circuits
  • Embedded System Design

FDP/ STTP/ Workshops/ Conferences Attended

Sl. No. Title Organization Period Outcome
1. GIAN Course on “Vogue Technologies on 5G & 5G+ Communication and Vehicular Technology” National Institute of Technology, Tiruchirappalli December 26, 2017- January 2, 2018 Understanding of 5G Technologies
2. Workshop on Design, Simulation and Research Application of Advanced Wireless Standards using EEsof National Institute of Technology, Tiruchirappalli July 23-25, 2015 Research and Simulation
3. IEEE International Conference on Circuits and Systems in Digital Enterprise Technology, ICCSDET Saintgits College of Engineering, Kottayam December 21-22, 2018 Research on Circuits and Systems
4. SMDP-C2SD Sponsored “Synopsys EDA Tools Training Programme” National Institute of Technology Tiruchirappalli January 5-10, 2017 EDA tools
5. IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICECCN Infant Jesus College of Engineering, Tuticorin March 25-26, 2013 Research in Communication

FDP/ STTP/ Workshops/ Conferences Organized 

Sl. No. Title Organization Period Outcome
1. TEQIP – III Sponsored International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks, IMICPW National Institute of Technology, Tiruchirappalli May 22-24, 2019 Research on Wireless Networks

Publications

Publication Type: Journal Article

Year of Publication Title

2019

Geethu S. and Gopalakrishnan, L., “Reconfigurable address generator for multi-standard interleaver”, Microprocessors and Microsystems, vol. 65, pp. 47-56, 2019.[Abstract]


This paper presents low-complex and novel techniques for designing reconfigurable architectures for multi-standard address generator and interleaver. The emphasis of this work is on hardware re-use, but it also focuses on optimizing the hardware to support multiple standards. A low-cost reconfigurable architecture for address generator and interleaver is proposed which operates in WLAN (802.11a/b/g and 802.11n), WiMAX (802.16e) and 3GPP LTE standards. A simple algorithm and a reconfigurable architecture that eliminates the computationally intricate mod function for LTE, and floor as well as mod function for WLAN/WiMAX, are proposed to reduce the hardware cost as well as implementation complexity. Novel architectures are also proposed to select the increment values for 16-QAM and 64-QAM schemes. A unique configurable subtracting sub-block for each modulation scheme is also presented. Software simulation is carried out to authenticate the functionality of the algorithm. The proposed reconfigurable architectures are realized on FPGA and tested on board. Synthesis results on Spartan-3 FPGA display 66% reduction in FPGA resource utilization and 74% increase in operating frequency compared to the cited address generators. Implementation results on Kintex UltraScale FPGA display a reduction of 34% in resource utilization and 20% in total on-chip power compared to the cited interleavers. This design is also implemented using 45 nm CMOS standard cell technology, and ASIC synthesis results of the reconfigurable address generator exhibit 76.4% improvement in data rate and 52.23% decrease in latency compared to the state-of-the-art address generators. The proposed multimode interleaver also exhibit 60.28% reduction in hardware complexity. © 2018 Elsevier B.V.

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2019

Geethu S., Madala, L. R., Gopalakrishnan, L., and Sellathurai, M., “Low-complex processing element architecture for successive cancellation decoder”, Integration, vol. 66, pp. 80-87, 2019.[Abstract]


A low-complexity design architecture for implementing the Successive Cancellation (SC)decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE)block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two's complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two's complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT)value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area. © 2019 Elsevier B.V.

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2013

Geethu S., Lakshminarayanan G., and Mathini Sellathurai, “Wide Band Spectrum Sensing Using Window Based Energy Detector For AWGN And Rayleigh Channels”, International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 5, 2013.[Abstract]


Cognitive Radio is an efficient technique to exploit the underutilized electromagnetic spectrum by introducing opportunistic usage of frequency bands that are not occupied by primary users. Spectrum sensing is a fundamental part of Cognitive Radio systems. A common low complexity technique for spectrum sensing is energy detection, however energy detection is known to fail in the presence of noise uncertainty. In this paper a window based energy detection technique that reduces the noise in the spectrum by averaging the power samples in the frequency domain is proposed to identify the presence of primary users. It is clearly shown that this window based technique improves the detection performance. Moreover the existence of primary users in sub bands of the wideband signal is also identified using this modified method. Simulations based on wideband signals in both fading as well as non fading environment are presented to verify the proposed technique.

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Publication Type: Conference Proceedings

Year of Publication Title

2018

Geethu S. and Gopalakrishnan, L., “Low-Complexity Successive Cancellation Decoder with Scan Chain”, 2018 International Conference on Circuits and Systems in Digital Enterprise Technology, ICCSDET 2018. Institute of Electrical and Electronics Engineers Inc., Kerala, 2018.[Abstract]


This paper presents a low complexity implementation of Successive Cancellation (SC) decoder architecture for the polar codes with scan chain for fault testing. Here a modified p-node is proposed at the last stage of SC decoder to decode 2-bits in a single clock cycle. The proposed architecture is designed and implemented on Kintex Ultrascale+ FPGA, xcku5p-ffv9676. The proposed SC decoder displayed 63% reduction in latency compared to conventional SC decoder. Implementation results displayed a significant reduction in resource utilization as well as on-chip power compared to prevailing SC decoders. © 2018 IEEE.

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2017

P. Ishwerya, Geethu S., and Lakshminarayanan, G., “An efficient hybrid spectrum sensing architecture on FPGA”, International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2017. Institute of Electrical and Electronics Engineers Inc., 2017.[Abstract]


Several spectrum sensing methods have been introduced to detect spectrum holes in the radio spectrum. Each method has its own strengths and limitations. No single spectrum sensing method works well in all scenarios. Since spectrum sensing is the key enabler in cognitive radio, it should be capable of reliably detecting the presence or absence of primary users. In this paper, we present a hybrid spectrum sensing architecture which combines the advantages of energy detection, autocorrelation based detection and covariance absolute value method (CAV). Based on the availability of information about the received signal and its correlation strength, one of the three methods is used for detection. The sensing time is increased since it has to decide on one among the three techniques. A methodology for deciding the most suitable technique is also proposed. The proposed hybrid architecture has been implemented on Xilinx Virtex 5 board (XC5VLX110T) and the results have been compared with those of the individual methods. © 2017 IEEE.

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2016

P. Ishwerya, Geethu S., and Lakshminarayanan, G., “Autocorrelation based spectrum sensing architecture on FPGA with dynamic offset compensation”, IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016.[Abstract]


In this paper, FPGA implementation of an autocorrelation based spectrum detector which is capable of overcoming DC offset and frequency offset problems is presented. There exist different non-idealities which deteriorate the performance of spectrum sensing algorithms developed for cognitive radio applications. Here, we analyze the effect of DC offset, frequency offset and their combined presence on spectrum sensing performance. The compensation factors which are incorporated make the algorithm tolerant against the two offsets. Algorithmic level verification has been done on Matlab. Hardware co-simulation has been done and the system has been tested with LTE 20 MHz signals. The algorithm has been implemented on Xilinx Virtex 5 board (XC5VLX110T) and the hardware results have been validated. © 2016 IEEE.

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2013

V. N. Kumar, Reddy, K. V., Geethu S., Lakshminarayanan, G., and Sellathurai, M., “Reconfigurable hybrid spectrum sensing technique for cognitive radio”, 2013 IEEE 8th International Conference on Industrial and Information Systems. 2013.[Abstract]


Due to massive entry of wireless services with inefficient spectrum resource utilization led to an apparent scarcity of usable radio bandwidth. Cognitive radio is well organized to utilize vacancy in the radio spectrum due to absence of primary user. Spectrum sensing i.e., detecting the presence of primary users in a licensed spectrum is the fundamental task in cognitive radio. This leads to emergence of a variety of approach to detect the presence of primary user. A two stage spectrum sensing can be used to mitigate the disadvantages of single stage detection and append the advantages of individual methods. However, the two stage detection increases the hardware and time taken to sense the spectrum. In our work, the two stage detection algorithm that was originally presented in the work of Geethu and Narayanan (2012) is efficiently implemented on Xilinx xc5vlx110t-1ff1136 FPGA using Dynamic Partial Reconfiguration (DPR) approach. The proposed architecture shows hardware improvement in terms of area and reconfiguration time over the conventional single stage detection techniques.

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2013

Geethu S. and Lakshminarayanan, G., “A novel selection based hybrid spectrum sensing technique for cognitive radios”, IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN. IEEE, 2013.[Abstract]


Cognitive radio is a solution for the spectral crowding problem by introducing opportunistic usage of frequency bands that are not occupied by licensed primary users. Spectrum sensing is the most important task of cognitive radio which identifies the existence of the primary users in the frequency band under consideration. Energy detector (ED) is one of the simplest and basic methods for spectrum sensing but it suffers from noise uncertainty problem. Covariance Absolute Value (CAV) is another spectrum sensing method which is based on the statistical covariance of the received signal but it works well only if the signal samples are highly correlated. Hence another novel selection based hybrid spectrum sensing method is proposed which combines the advantages of both the methods. Simulation results prove that the novel selection based spectrum sensing method outperforms both the energy detection as well as CAV method and identifies the spectrum hole irrespective of the nature of the signal under consideration. More »»

2012

Geethu S. and Narayanan, G. L., “A Novel High Speed Two Stage Detector for Spectrum Sensing”, Proceedings of ICCCS-2012 , vol. 6. Procedia Technology, pp. 682 - 689, 2012.[Abstract]


Large numbers of spectrum sensing techniques have been introduced to detect the presence of primary users. Though each technique has its own advantages and disadvantages, the disadvantages associated with one leads to the development of the others. A two stage detector for spectrum sensing can be used to overcome the limitations of a single stage detection technique and to combine the advantages offered by the individual methods. However, a two stage spectrum sensing technique increases the time taken for sensing a spectrum. In this paper, a novel method is proposed that effectively decreases the time taken for sensing the spectrum whereas meeting the required detection capabilities. Simulation results have been used to show that the proposed method leads to larger savings in time compared to the already available two stage detection method for spectrum sensing.

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Faculty Research Interest: