Qualification: 
Ph.D
v_rajath@blr.amrita.edu
Phone: 
+91-7259520557

Dr. Rajath Vasudevamurthy currently serves as Assistant Professor(SG) at the department of Electronics and Communication Engineering, Amrita School of Engineering, Bengaluru Campus. He has spent seven months as a visiting researcher at the Department of Signal Processing, KTH, Stockholm (Sweden) and a year as Post-Doctoral Researcher at the Department of Computer Science, Pennsylvania State University, State College, PA.
 

EDUCATION

  • 2014: Ph. D. 
    Indian Institute of Science, Bengaluru
  • 2007: B. E. 
    R. V. College of Engineering, Bengaluru
     

Publications

Publication Type: Journal Article

Year of Publication Publication Type Title

2014

Journal Article

Dr. Rajath Vasudevamurthy, Das, P. K., and Amrutur, B., “Time-Based All-Digital Technique for Analog Built-in Self-Test”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 334-342, 2014.[Abstract]


A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry. More »»

2011

Journal Article

B. Amrutur, Das, P. K., and Dr. Rajath Vasudevamurthy, “0.84 ps Resolution Clock Skew Measurement via Subsampling”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, pp. 2267-2275, 2011.[Abstract]


An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are subsampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of ±1 fan-out-of-4 (FO4) delay, ±3σ resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks. More »»

Publication Type: Patent

Year of Publication Publication Type Title

2014

Patent

Dr. Rajath Vasudevamurthy and Amrutur, B., “System and method for Built-In Self Test (BIST) in an integrated circuit”, U.S. Patent PCT/IB2012/0574622014.[Abstract]


Embodiments of the disclosure relate to a method and system for Built-in-Self- Test of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of sub-sampled signals, thus giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. More »»

Publication Type: Conference Paper

Year of Publication Publication Type Title

2013

Conference Paper

Dr. Rajath Vasudevamurthy and Amrutur, B., “Multiphase Technique to Speed-up Delay Measurement via Sub-sampling”, in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013.[Abstract]


A multi-phase technique for speeding up the measurement of delays via sub-sampling is presented. Measurement of delays using the sub-sampling approach leads to a very simple system implementation, and also provides the opportunity of trading off between bandwidth and accuracy. Such a scheme becomes extremely attractive for deep sub-micron processes due to its highly-digital nature and the ability to offer compact, low power, mixed-signal implementation alternatives. However, a drawback is the amount of averaging (measurement time) that is needed to get accurate results. A multiphase input clock scheme is proposed to address this issue, especially for the measurement of small delays, thereby speeding up the overall measurement. Simulation results from MATLAB Simulink confirm the speedup achieved upto a factor of eight with an eight-phase clock input for sufficiently small fixed test delays and also an improvement in SNR upto 11dB for slowly varying test delays. More »»

2011

Conference Paper

Dr. Rajath Vasudevamurthy, Das, P. K., and Amrutur, B., “A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test”, in 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011.[Abstract]


A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds. More »»

207
PROGRAMS
OFFERED
6
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS