Amrita Presents at IEEE Conference 2009 ICCSIT
Amrita students and faculty recently traveled to Beijing in China to present papers at the 2nd IEEE International Conference on Computer Science and Information Technology (ICCSIT). Only about 30% papers of the 2840 submissions received were selected for presentation. These included five papers* from Amrita faculty and students. “Most participants were graduate or doctorate level students,” later shared Br. Rajesh Kannan who traveled to Beijing from Amritapuri with 7 of his final-year B Tech students to present four of the five papers selected from Amrita. The papers all focused on different aspects of Low Power VLSI Designs.
In addition to teaching classes to B Tech students, Rajesh is also currently enrolled in the M Tech program at Amrita University. “Some paper presentations were from industry. People were wondering when they heard that undergraduate students had also come from India for paper presentation.” Rajesh and his B Tech students have presented papers at other international conferences before. In November 2009, they will travel to Malaysia to present at the 2009 ICCTD Conference.
In addition to Rajesh and his students, Ms. N. Lalithamani, Assistant Professor in the Department of Computer Science and Engineering at the Amrita School of Engineering, Coimbatore, was also at the same conference in Beijing to present a paper she had co-authored with Dr. K. P. Soman, Director of the CEN Research Center.
“An unswerving information security mechanism is the need of the hour for fighting the escalating enormity of identity theft in our society. Besides cryptography being a dominant tool in attaining information security, one of the key confronts in cryptosystems is to preserve the secrecy of the cryptographic keys. The incorporation of biometrics with cryptography will be an effective solution to this problem.” (See Complete Paper Abstract)
All five papers will be included in the conference proceedings published by IEEE, and will be listed in the IEEE Xplore. They will also be indexed by both EI (Compendex) and ISI Proceeding (ISTP). We congratulate the faculty and students on this achievement.
Rajesh Kannan Megalingam, Shekhil Hassan T, Vivek P, Ashwin Mohan and Tanmay Rao M, Power Consumption Reduction in CPU Datapath using a Novel Clocking Scheme
Power consumption and performance are crucial factors that determine the reliability of a CPU. In this paper, we discuss some techniques that can be used for Instruction Level Parallelism that enhances the performance of the CPU by reducing the CPI there by reducing power consumption. We have also discussed the power saving scheme using proper clocking strategies. We have mainly focused on implementing the simplified RISC pipeline datapath in HDL using two different clocking schemes to reduce the power consumption. We have adopted a new method which uses dual edge triggered clock that can decrease the power consumption of a pipelined datapath considerably, without sacrificing the throughput of the CPU. Finally, we have given the experimental result for our implementation of simplified RISC datapath.
Rajesh Kannan Megalingam, Nived Krishnan, Arjun Ashok V and Arunkumar M, Highly Power Efficient, Uncompromised Performance Cache Design Using Dual-Edged Clock.
Dynamic power dissipation is a field where research has been conducted to reduce energy consumption in present clocked systems. Here we discuss the various tiers of power management in design followed by a treatise on dynamic power dissipation in CMOS circuits and power efficient cache designs under research. We propose a technique to reduce the clock frequency of circuits without compromising the performance. This is achieved by using a dual-edged clock for the operation, allowing the operating frequency to be halved, which immediately translates into a tremendous gain in power efficiency. The applications of this technique in processor caches are also studied. The designs proposed herein were implemented using Verilog HDL and the power requirements analyzed using Xilinx XPower 10.1. Experimental results and the conclusions drawn are included.
Rajesh Kannan Megalingam, Deepu K B, Iype P Joseph and Vandana Vikram, Phased Set Associative Cache Design For Reduced Power Consumption.
In this paper, improvised versions of the set associative cache accessing technique have been proposed to reduce power consumption. In phased cache the cache access process is divided into two phases. In the first phase, all the tags in the set are examined in parallel. In the next phase, if there is a hit, then a data access is performed for the hit way. The average energy consumption is reduced as we are not accessing the data together with tag in each phase. Behavioral implementation of these mechanisms was carried out using Verilog HDL. Synthesis of the design was done in Xilinx 10.1. The Xilinx Xpower analyzer is used to find the power consumption. The results show an average of 41% reduction in power consumption as compared to the conventional sequential set associative cache and an average of 21% power reduction as compared to conventional parallel set associative cache architecture.
Aswathy Prasad, Kamya Krishnan, Karthika, Parvathy and Rajesh Kannan Megalingam, Low Power Losssless Compression of Real Time Mpeg4 Video Encoding And Decoding Using Vhdl And Matlab.
This paper presents a simple model of complex real time MPEG-4 video encoding and decoding using simple techniques in VHDL and MATLAB that provide reasonable compression while using less power and resources on FPGA. This implementation works on low power and less number of clock cycles. The basic video codec module consists of a video encoder and a decoder. The encoder module consists of blocks for temporal modeling, spatial modeling and Entropy encoding. Temporal block has a difference block whereas spatial block consists of 2-D DCT, Quantizer and a 2-D IDCT. Sample frames of real time video have been processed using the codec module resulting in an average compression of 64.6%. This can be applied in areas where low bit rate, high quality video is required. The first 5 sections in this paper represent the concepts and theories used, section 6 onwards represents the actual implementation of the module.
N. Lalithamani, Dr. K. P. Soman An Effective Scheme for Generating Irrevocable Cryptographic Key from Cancelable Fingerprint Templates.
An unswerving information security mechanism is the need of the hour for fighting the escalating enormity of identity theft in our society. Besides cryptography being a dominant tool in attaining information security, one of the key confronts in cryptosystems is to preserve the secrecy of the cryptographic keys. The incorporation of biometrics with cryptography will be an effective solution to this problem.
Recently generating cryptographic key from biometrics has gained enormous popularity in research community due to its improved performance in providing security. Nevertheless, a biometric is connected with a user and cannot be altered. Thus, when a biometric identifier is compromised, it is lost everlastingly and probably for every application where that particular biometric is employed.
Cancelable biometrics intends to resolve this by building revocable biometric templates. In this paper, we have proposed an effective scheme for generating irrevocable cryptographic key from cancelable fingerprint templates. Initially the minutiae points are extracted from the fingerprints. Afterwards, cancelable templates are generated and irrevocable keys are extracted from the cancelable templates. As the cryptographic key is generated in an irreversible manner, obtaining cancelable fingerprint templates and original fingerprints from the generated key is impossible. We have evaluated the effectiveness of our scheme using fingerprints from publicly available sources. We have also presented the security analysis of the proposed scheme.
August 26, 2009
Schools of Engineering, Amritapuri and Coimbatore