AmritaWNA Engages in Collaborative Indo-Japanese Mobility Project
Amrita Center for Wireless Networks and Applications (AmritaWNA) and the VLSI Design and Education Center (VDEC) at the University of Tokyo have recently embarked on a 24-month international cooperative science program funded by the Department of Science and Technology (DST), Government of India, and the Japan Society for the Promotion of Science (JSPS) in order to develop a next generation VLSI/SoC hardware for wireless networks and security. The Indo-Japanese Mobility Project was approved by the Department of Science & Technology (DST), Government of India, in order to facilitate on-site collaboration and face-to-face communication between scientists from Amrita University and the University of Tokyo.
The principal investigators of the project are Dr. Maneesha V. Ramesh, Director, AmritaWNA, and Dr. Masahiro Fujita, Professor, VLSI Design and Education Center (VDEC), University of Tokyo. Other collaborators from Amrita University include Dr. Bibhudatta Sahoo, Associate Professor, Electronics and Communication Engineering, Amrita School of Engineering; Dr. Anand Ramachandran, Associate Professor, AmritaWNA; Dr. Sundar Gopalan, Associate Professor and Chairperson, Electronics and Communication Engineering, Amrita School of Engineering; Dr. Krishnashree Achuthan, Director, Amrita Center for Cybersecurity; Prof. Balaji Hariharan, Associate Professor, AmritaWNA and Dr. Shyam Diwakar, Assistant Professor, Amrita School of Biotechnology.
Initiated by the Chancellor of Amrita University, Sri. Mata Amritanandamayi Devi, the new project will leverage the University’s expertise in analog, digital, and embedded system designs and the University of Tokyo's expertise in algorithms and techniques in order to build programmable hardware. With this collaboration, AmritaWNA will have the opportunity to fabricate its semiconductor design via the facilities available at the University of Tokyo.
In order to evaluate the design environment, AmritaWNA researchers will apply the new VLSI/SoC designs to wireless communication systems utilized for the early detection of landslides. The Center has already been recognized world-wide for its innovation and has already received funding from governmental agencies such as the Ministry of Earth Sciences (MoES), the Department of Science and Technology (DST) and the Department of Electronics and Information Technology (DeitY).
In this project, AmritaWNA researchers, in conjunction with researchers from VDEC, will develop an enhanced, energy efficient and highly accurate VLSI/SoC sensor network system that can be used for the early detection of landslides. Furthermore, AmritaWNA and University of Tokyo researchers will develop customized, high performance, computing systems where specific applications can be accelerated in comparison to multi-microprocessor based computation servers. The target of such acceleration would be based on biological modelling such as neural models. The biological research group at Amrita has already acquired a significant amount of research on new neural modelling, modelling which requires intensive computations. Such computations can be sped up with partial hardware implementations.
The current collaborative project focuses on building robust, safety-critical, and real-time embedded systems. Two distinct design schemes are prevalent in these embedded systems: event-triggered and time-triggered. Though event-triggered systems are prevalent due to their high responsiveness to events, safety-critical real-time systems are often built as time-triggered systems. The key advantage of the time-triggered design is its deterministic execution and simplicity. The main research work is to combine time and event concepts to increase the overall robustness of a system.
June 19, 2014
AmritaWNA, Amritapuri Campus