Publication Type:

Journal Article

Source:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 12, p.2267-2275 (2011)

Keywords:

all-digital on-chip clock skew measurement system, Arithmetic difference, asynchronous subsampling, clock jitter, clock skew measurement, Clocks, conventional XOR, delay, FM modulation, FO4 delay, frequency modulation, histogram analysis, histogram approach, Histograms, Jitter, near-frequency asynchronous sampling clock signal, robustness, semiconductor device measurement, Signal sampling, size 65 nm, subsampling, time 0.65 ps, time 0.84 ps, time-to-digital converter, timing jitter

Abstract:

An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are subsampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of ±1 fan-out-of-4 (FO4) delay, ±3σ resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks.

Cite this Research Publication

B. Amrutur, Das, P. K., and Dr. Rajath Vasudevamurthy, “0.84 ps Resolution Clock Skew Measurement via Subsampling”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, pp. 2267-2275, 2011.

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