An 8 Bit 4 GS/s 120 mW CMOS ADC
Publication Type:Journal Article
Source:IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers Inc., Volume 49, Number 8, p.1751-1761 (2014)
Keywords:Algorithms, Analog to digital conversion, calibration, CMOS integrated circuits, Electric delay lines, Error detection and correction, interleaving, Pipelined analog-to-digital converter, Timing calibration, Variable delay lines
A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology. © 2014 IEEE.
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