A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology. © 2014 IEEE.
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Ha Wei, Zhang, Pbc, Sahoo, B. Dd, and Razavi, Ba, “An 8 Bit 4 GS/s 120 mW CMOS ADC”, IEEE Journal of Solid-State Circuits, vol. 49, pp. 1751-1761, 2014.