Publication Type:

Journal Article

Source:

IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers Inc., Volume 49, Number 8, p.1751-1761 (2014)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84905257511&partnerID=40&md5=249b395599726567ace1c27aad3e21d6

Keywords:

Algorithms, Analog to digital conversion, calibration, CMOS integrated circuits, Electric delay lines, Error detection and correction, interleaving, Pipelined analog-to-digital converter, Timing calibration, Variable delay lines

Abstract:

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology. © 2014 IEEE.

Notes:

cited By (since 1996)0

Cite this Research Publication

Ha Wei, Zhang, Pbc, Sahoo, B. Dd, and Razavi, Ba, “An 8 Bit 4 GS/s 120 mW CMOS ADC”, IEEE Journal of Solid-State Circuits, vol. 49, pp. 1751-1761, 2014.