A four-channel time-interleaved pipelined ADC employs a new timing calibration technique to suppress mismatch-induced spurs and achieve a Nyquist-rate SNDR of 44.4 dB. Designed in 65-nm CMOS technology, the ADC draws 120 mW, providing an FOM of 219 fJ per conversion step. © 2013 IEEE.
cited By 0; Conference of 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference Date: 22 September 2013 Through 25 September 2013; Conference Code:101988
Ha Wei, Zhang, Pb, Sahoo, BcDatta, and Razavi, Ba, “An 8-Bit 4-GS/s 120-mW CMOS ADC”, in Proceedings of the Custom Integrated Circuits Conference, San Jose, CA, 2013.