An 8 Bit 4 GS/s 120 mW CMOS ADC.
Publication Type:Journal Article
Source:Journal of Solid-State Circuits, IEEE, Volume 49, Number 8, p.1751–1761 (2014)
A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB
and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.