This paper describes the characteristics and analysis of accumulator which are obtained from simulations performed in Cadence (Virtuoso) and done the layout. The sizing strategy used for sizing the standard cell blocks used to build the accumulator result in a minimum propagation delay between input and output. © Springer India 2016.
cited By 0; Conference of International Conference on Artificial Intelligence and Evolutionary Computations in Engineering Systems, ICAIECES 2015 ; Conference Date: 22 April 2015 Through 23 April 2015; Conference Code:164469
N. C. Balan and Jose, A. A., “Accumulator design in cadence 90 nm technology”, Advances in Intelligent Systems and Computing, vol. 394, pp. 273-284, 2016.