Publication Type:

Journal Article




<p>Difference between speed of processorand memory is increasing with advent of every&nbsp;new technology. Chip Multi Processors (CMP)&nbsp;have further increased the load on the memory&nbsp;hierarchy. So it has become important to manage&nbsp;on-chip memory judiciously to reduce average&nbsp;memory access time. The previous research has&nbsp;shown that it is better to have a shared cache at&nbsp;the last level of on-chip memory hierarchy.&nbsp;Sharing last level of cache gives rise to a new&nbsp;category of cache misses; those were not present&nbsp;in uniprocessor, called “inter-processor misses”.&nbsp;This paper proposes a technique to eliminate&nbsp;inter-processor misses by giving replacement&nbsp;ownership of a block to a processor who brought&nbsp;it into the cache. This reduction in interprocessor&nbsp;misses, which constitutes 40% of over&nbsp;all misses, will result in performance&nbsp;improvement. Also two different ways of&nbsp;relinquishing the ownership of a block are being&nbsp;proposed, so that if some other processor, other&nbsp;than owner, can make use of the block in a more&nbsp;efficient way, ownership will be transferred to the&nbsp;new processor.</p>

Cite this Research Publication

R. Kumar, Chaturvedi, N., and Sudarshan, T. S. B., “Adaptive Block Pinning for Multi-core Architectures”.