Analysis of thermal noise and noise reduction in CMOS device

Publication Type:

Conference Paper

Authors:

M. Archanaa; Karthigha Balamurugan

Source:

International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 (2014)

ISBN:

9781479949816

Accession Number:

14665801

Keywords:

CMOS, CMOS integrated circuits, CMOS noise, equivalent noise models, equivalent noise voltage, gate resistance, integrated circuit modelling, integrated circuit noise, Logic gates, mathematical model, Multi-finger gate structures, multifinger gate structure, nMOS, noise, noise reduction, Power dissipation, Radio frequency, Resistance, RF, short channel effect, small signal equivalent, Small signal noise model, Thermal noise

Abstract:

Advanced CMOS technology assures CMOS device as a good choice for physical realization of RF applications. But as scaling progresses, noise and short channel effect start to deteriorate the device performance, thus increasing the power dissipation. This work focuses on the analysis of thermal noise by varying the gate resistance and frequency. Equivalent noise voltage is calculated for various extracted gate resistance and the effect of distributed gate resistance due to wider channel MOS is analyzed. Thermal noise is reduced using multifinger gate structure when compared to conventional nMOS. A complete small signal equivalent of nMOS along with augmented equivalent noise models is discussed.

Cite this Research Publication

M. Archanaa and Karthigha Balamurugan, “Analysis of thermal noise and noise reduction in CMOS device”, in International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 , 2014.

 
          
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