Decimal arithmetic is gaining more and more importance in business, commercial and financial applications due to error free and high speed computations. In this work, high speed radix10 divider architecture has been proposed to reduce the delay. This paper presents a modified architecture in which intermediate results are utilized to perform the high speed division. The modified architecture is simulated for different numbers of bits. Synthesis results show that the modified architecture implemented in 180nm technology has reduced delay when compared to digit recurrence with constant digit selection function architecture which is the fastest of existing architectures.
cited By 0; Conference of 6th International Conference on Computer Communication and Informatics, ICCCI 2016 ; Conference Date: 7 January 2016 Through 9 January 2016; Conference Code:121903
S. Neethu, S. Agrawal, and Murty, N. S., “An architecture for high speed Radix10 division”, in 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, 2016.