A design for a white Gaussian noise generator (WGNG) is modified and implemented as a 0.18-μm CMOS digital ASIC for high-speed communication channel emulation. The original design was implemented using an FPGA. The goal of the work presented is to enhance the performance of the WGNG in order to achieve emulation of high-speed communication standards unattainable by the FPGA implementation. This is accomplished by pipelining the original design and implementing it using an ASIC. A layout is generated, based on a standard digital design flow provided by the Canadian Microelectronics Corporation (CMC). This implementation achieves an output rate of 182 Msamples/sec, which exceeds the speed of the original FPGA implementation by more than seven times.
E. Fung, Leung, K., Parimi, N., Dr. Madhura Purnaprajna, and Gaudet, V. C., “ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator]”, in IEEE Workshop on Signal Processing Systems, 2004. SIPS 2004. , 2004.