Hash algorithms are a class of cryptographic primitives used for fulfilling the requirements of integrity and authentication in cryptography. In this paper, we propose and present the ASIC implementation of 'HashChip', a hardware architecture aimed at providing a unified solution for three different commercial MDC (manipulation detection codes) hash primitives, namely MD5, SHA1 and RIPEMD160. The novelty of the work lies in the exploitation of the similarities in the structure of the three algorithms to obtain an optimized architecture. The performance analysis of a 0.18μm ASIC implementation of the architecture has also been done.
T. S. Ganesh and Sudarshan, T. S. B., “ASIC implementation of a unified hardware architecture for non-key based cryptographic hash primitives”, in Information Technology: Coding and Computing, 2005. ITCC 2005. International Conference on, 2005.