Publication Type:

Conference Paper

Source:

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) (2016)

Keywords:

Cache coherence, cache coherence approach, cache coherence mechanism, Cache memory, cache storage, Coherence, Directory, Flat-directory, Hardware, Hierarchical directory, memory hierarchy, multicore design, Multicore processing, multicores, private/shared, Program processors, Protocols, Scalability, Snoopy

Abstract:

Cache memory is a main component of memory hierarchy which plays an important role in the overall performance of the system and in the design of multicores. Multicores with shared memory architecture are used to satisfy increasing performance demands, which in turn is limited by cache coherence problem. This survey gives a comprehensive view and analysis on the various cache coherence mechanisms in modern architectures. With the availability of several cache coherence mechanisms, the selection of an approach depends on various parameters under consideration like storage, scalability, traffic, latency, energy etc. This article surveys the different cache coherence approaches and future design directions for improving the cache coherence mechanism.

Cite this Research Publication

N. Parvathy, Bhargavi R. Upadhyay, and Sudarshan, T. S. B., “Cache coherence: A Walkthrough of Mechanisms and Challenges”, in 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016.

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