Multipliers form an unavoidable part of almost all mathematical calculations. With the advent of complex digital signal processing algorithms, the requirement of fast multipliers became important. Since multipliers play a key role in the dsp applications, the overall performance of the application or device depends on their performance. In this paper we are discussing about the multibit recoding of the signed two’s complement binary numbers and how this can be used in the implementation of multipliers. The implementation of Wallace tree adder stages for accumulating the partial products is done. With the availability of fast adders like carry save adder and carry look ahead adder, efficient design of multipliers is carried out. This increases the speed and performance of parallel multipliers. Here signed digit representations like radix 4,radix 8 and radix 16 are discussed. Overlapping of vectors is performed for recoding a two’s complement binary number. Ak+1 bit recoding will result in a signed digit representation of the binary numbers in radix 2k, using digits -2k-1 to +2k-1 including 0. The minimum time period and the maximum frequency for the multipliers in which recoding process is done is calculated. Thus a comparative analysis is done for the different recoding techniques by implementing them in multiplier circuit. © Research India Publications.
cited By 0
N. Thaha, “A comparative study on multibit recoding in multipliers”, International Journal of Applied Engineering Research, vol. 10, pp. 476-479, 2015.