Publication Type:

Conference Paper

Source:

2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Mangalore, Karnataka, p.239-243 (2010)

ISBN:

9781424466535

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-77958579739&partnerID=40&md5=aed03334db5021787cbf4cd55acfc36e

Keywords:

Add algorithms, Algorithms, Computer hardware, Data throughput, Digital computers, Efficient algorithm, Hardware signal processing, Hyperbolic functions, Information systems, Iterative CORDIC, Logarithmic functions, Modelsim, Parallel CORDIC, Pipelined CORDIC, Rotation, Signal processing, Synthesis tool, Vector rotation, Vectors, Xilinx FPGA

Abstract:

Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (COrdinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. The paper compares the different CORDIC architectures with respect to their area, speed, and data throughput performance especially in three different major styles iterative, parallel and pipelined structures. All three designs were designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. ©2010 IEEE.

Notes:

cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@7ce23835 ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@67d85fa0 Through org.apache.xalan.xsltc.dom.DOMAdapter@2e6e36a3; Conference Code:81949

Cite this Research Publication

R. Bhakthavatchalu, Sinith, M. S., Nair, P., and Jismi, K., “A comparison of pipelined parallel and iterative CORDIC design on FPGA”, in 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Mangalore, Karnataka, 2010, pp. 239-243.