Publication Type:

Conference Paper

Source:

2019 International Conference on Communication and Signal Processing (ICCSP), IEEE, Chennai, India, India (2019)

Keywords:

C++ code, C++ languages, Computational analysis, Computer architecture, Edge detection, Execution time, Field programmable gate arrays, Hardware, hardware-software codesign, High Level Synthesis, High-level synthesis, Image edge detection, Intense Computing Algorithm, PL, processing system, program logic, PS, RTL, Sobel edge detection, Sobel Edge Detection Algorithm, Software, Software algorithms, Xilinx Vivado HLS 2015.3 design suite

Abstract:

The main aim of the project is to compare the variations in execution time of an Intense Computing Algorithm in Software (PL-Program Logic) and RTL (PS-Processing System). This is done by simulating and synthesizing a chosen algorithm (here we have chosen the Sobel Edge Detection Algorithm) in Xilinx Vivado HLS 2015.3 design suite. In the initial phase the C++ code for the Sobel Edge Detection is developed in Xilinx Vivado HLS. The source code is then simulated using the test bench and the execution time is evaluated. The second phase involves developing the RTL part of the algorithm. This is done by the method of High-Level Synthesis (HLS) in Xilinx Vivado HLS. The RTL counterpart thus generated is then simulated and the execution time is calculated. The execution time for both the PL and PS implementations are compared and analyzed.

Cite this Research Publication

Rajesh Kannan Megalingam, Karath, M., Prajitha, P., and Pocklassery, G., “Computational Analysis between Software and Hardware Implementation of Sobel Edge Detection Algorithm”, in 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, India, 2019.

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