Publication Type:

Journal Article

Source:

International Journal of Engineering and Technology, Volume 7, Issue 3, p.973-984 (2015)

URL:

https://doaj.org/article/cba3b2b27fd04fd185141640d6735417

Keywords:

At-speed testing, boundary scan, DFT, hardware security, Logic BIST, Scan chain

Abstract:

A technique to provide programmable secure access to the scan based Logic Built in Self- Test (BIST) structures is proposed. Joint Test Access Group (JTAG) interface is the major test access method used in VLSI IC’s. At the same time, it can be misused as a means to access and hack the hardware circuitry of the IC. It is addressed in this method to prevent unauthorized users from hacking the JTAG interface and interfering in the Logic BIST test functions. A two stage, multiple crypto algorithms based separate authorization schemes are used. A configuration register can be programmed to select the level of security to a specific user group. Different crypto algorithms can be chosen, with user specifiable key lengths. A challenge response protocol is employed to authenticate the user and corresponding accessibility. All the features included are compliant with the IEEE JTAG standard 1149.1. This technique is applied on ISCAS-89 and ISCAS-99 benchmark designs with the help of Cadence Encounter true time 13.1 design automation tools and results are shown. A small amount of (less than 2 to 5%) increase in area reported for implementing the security features.

Cite this Research Publication

R. Bhakthavatchalu and M. Nirmala Devi, “Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture”, International Journal of Engineering and Technology, vol. 7, no. 3, pp. 973-984, 2015.