Publication Type:

Journal Article

Source:

International Journal of Embedded and Real-Time Communication Systems, Volume 3, Number 1, p.70-81 (2012)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84872918016&partnerID=40&md5=6fab7fbafa5199b58b3ecf726c2bc6e0

Abstract:

Network on chip (NoC) has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. In NoCs, the traditional routing schemes are routing packets through a single path or multiple paths from one source node to a destination node, minimizing the congestion in the routing architecture. Although these routing algorithms are moderately efficient, they are time dependent. To reduce overall data packet transmission time in the network, the authors consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, the authors have constructed a deadlock-free multi-dimensional path routing algorithm for minimizing the congestion in NoC. Copyright © 2011, IGI Global.

Notes:

cited By (since 1996)0

Cite this Research Publication

Kab Somasundaram and Plosila, Jc, “Deadlock free routing algorithm for minimizing data packet transmission in network on chip”, International Journal of Embedded and Real-Time Communication Systems, vol. 3, pp. 70-81, 2012.