Publication Type:

Journal Article

Source:

International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 55, p.621-625 (2015)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84942326010&partnerID=40&md5=9539a84bab3e4159a9879ea0a5e5cd8a

Abstract:

Memory arrays are the essential building block inmany of present day digital systems. Therefore understanding the various aspects of designing an SRAM cell is very essential in designing other digital circuits as well. Memory elements consume a larger part of the area in most of the present day integrated circuits. The projects aims at designing and implementing a compact 1KB SRAM cell reducing the area. The circuit was designed in Cadence Virtuoso using the 90nm technology library. One of the most important factor that should be considered while designing any memory circuit is Static Noise Margin (SNM). Therefore static noise margin analysis of the basic 6T SRAM cell is also performed to analyse the circuit for read and write margins. Mat Lab was used for plotting the response of the circuit for various operations such as read, write and hold. © Research India Publications.

Notes:

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Cite this Research Publication

R. S. Reghu and Jyothilekshmi, P., “Design of 1KB SRAM and static noise margin analysis”, International Journal of Applied Engineering Research, vol. 10, pp. 621-625, 2015.