Publication Type:

Conference Proceedings

Source:

International Conference on Electronics and Communication Systems (ICECS), 2014 , Coimbatore (2014)

Keywords:

CMOS integrated circuits, CMOS technology, hardware description languages, integrated circuit design, integrated circuit interconnections, mesh of grid, mesh-of-grid topology, Network on Chip, network on chips, Network routing, Network topology, Network-on-chip, Ports (Computers), router, routing, Routing protocols, Switches, synopsys design vision, System-on-chip, Topology, Verilog HDL, virtual channel router

Abstract:

<p>Network on Chips (NoCs) has now replaced the bus based architectures for communication between different cores in a multiprocessor System on Chip (SoC). NoC integrates SoCs in a better manner. It has the advantage of good scalability and high bandwidth. The communication on NoC is carried out by means of routers. Routers are the back bone of NoC. The design of routers is different for different topologies. In this paper, a Mesh-of-Grid topology is considered. A virtual channel router for mesh of grid topology of NoC is presented here. Area and Power is synthesized for the virtual channel router using Synopsys Design Vision. The experimental results show that the area and power will increase if the bit size of flit is increased.</p>

Cite this Research Publication

N. V. Anjali and Dr. Somasundaram K., “Design and evaluation of virtual channel router for mesh-of-grid based NoC”, International Conference on Electronics and Communication Systems (ICECS), 2014 . Coimbatore, 2014.

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