Publication Type:

Conference Paper

Source:

2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, Institute of Electrical and Electronics Engineers Inc. (2015)

ISBN:

9781479979264

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84925664642&partnerID=40&md5=26be0d6c17549338c03c964544f5728b

Keywords:

Adders, Computer architecture, Design, Design compiler, Digital arithmetic, Digital signal processors, Field programmable gate arrays (FPGA), Floating point numbers, integrated circuit design, Kogge-Stone adder, Pipelines, Radix-4, Signal processing, Trees (mathematics), Wallace- tree structures

Abstract:

Floating point numbers are the quantities that cannot be represented by integers, either because they contain fractional values or because they lie outside the range re presentable within the system's bit width. Multiplication of two floating point numbers is very important for processors. Architecture for a fast floating point multiplier yielding with the single precision IEEE 754-2008 standard has been used in this project. The floating point representation can preserve the resolution and accuracy compared to fixed point. Pipeline is a technique where multiple instructions are overlapped in execution. Multiple operations performed at the same time by pipeline will increase the instruction throughput. In several high performance computing systems such as digital signal processors, FIR filters, microprocessors, etc multipliers are key components. The most important aim of the design is to make the multiplier quicker by decreasing delay. Decrease of delay can be caused by propagation of carry in the adders having smallest amount power delay constant. © 2015 IEEE.

Notes:

cited By 0; Conference of 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015 ; Conference Date: 8 January 2015 Through 10 January 2015; Conference Code:111173

Cite this Research Publication

N. V. Sunesh and Sathishkumar, P., “Design and implementation of fast floating point multiplier unit”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.