Cascaded Integrator Comb (CIC) filters are widely used in Multirate signal processing as a filter in both decimator (decrease in the sampling rate) and interpolator (increase in the sampling rate). This paper discusses the architecture, design and implementation aspects of decimator and interpolator using CIC filter and comparison between the results in hardware and simulations. The hardware is implemented in FPGA and verified with Modelsim & Lab VIEW simulation results. CIC filters serve as powerful anti aliasing agents before decimation and anti- imaging agents for interpolated signals. This paper also discusses about the method to improve the CIC attenuation. CIC Decimator and Interpolator were coded in Verilog, simulated using Modelsim simulator and Lab VIEW and implemented using Xilinx FPGA device.
Dr. Ramesh Bhakthavatchalu, Karthika, V. S., and Ramesh, L., “Design and Implementation of Improved Attenuation CIC Decimator and Interpolator in FPGA”, Int. J. on Recent Trends in Engineering and Technology, vol. 6, pp. 18-22, 2011.