Publication Type:

Conference Paper

Source:

2017 International Conference on Computer Communication and Informatics, ICCCI 2017, Institute of Electrical and Electronics Engineers Inc. (2017)

ISBN:

9781467388542

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85041442545&doi=10.1109%2fICCCI.2017.8117757&partnerID=40&md5=6ffa274286c38fd09af70e6571745740

Keywords:

60 GHz, Amplifiers (electronic), CMOS integrated circuits, Drain current, Forward body bias, Forward body biasing, gain variability, integrated circuit design, LNA design, Low noise amplifier designs, Low noise amplifiers, Low noise figure, Minimum noise figure, Noise figure

Abstract:

<p>This paper presents a low power, high gain low noise amplifier (LNA) design using current re-use inductors and complementary MOS structure. Gain variability has been achieved using forward body bias technique applied in the amplifying transistor. Using current re-use inductors at the drain of the complementary MOS structure, drain current is shared between PMOS and NMOS. The width of amplifying transistor is chosen to give minimum noise figure and good input matching. The observations show that the gain obtained by the proposed structure is 8.05dB with low noise figure of 2.14dB. The supply voltage used in the LNA design is 1.1V resulting in a power consumption of 2.607mW. © 2017 IEEE.</p>

Notes:

cited By 0; Conference of 7th International Conference on Computer Communication and Informatics, ICCCI 2017 ; Conference Date: 5 January 2017 Through 7 January 2017; Conference Code:132680

Cite this Research Publication

B. M. Ninan and Balamurugan, K., “Design of CMOS based low noise amplifier at 60 GHz and it's gain variability through body biasing”, in 2017 International Conference on Computer Communication and Informatics, ICCCI 2017, 2017.

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