Publication Type:

Journal Article

Source:

World Applied Sciences Journal, Volume 20, Number 8, p.1159-1165 (2012)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84872823735&partnerID=40&md5=ac50c51a4cee60c7e714b34525a93835

Abstract:

Reversible logic gates provide power optimization which can be used in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a Novel reversible 4:2 compressor, 6:2 compressor and 9:2 compressor designed from the DKGP gate that can work singly as a reversible full adder/full subtractor. These are later used to design a novel 8x8 reversible Wallace tree multiplier. This is the first attempt to design a reversible 6:2 and 9:2 compressors and a reversible Wallace tree multiplier using the above said circuits as far as our knowledge is concerned. Thus, this paper provides a threshold to build more complex systems using reversible logic. © IDOSI Publications, 2012.

Notes:

cited By (since 1996)0

Cite this Research Publication

Da Krishnaveni, Priya, MbGeetha, and Baskaran, Kc, “Design of an efficient reversible 8x8 wallace tree multiplier”, World Applied Sciences Journal, vol. 20, pp. 1159-1165, 2012.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS