In this paper, a multirate sampling filter is designed by using multiple constant multiplication (MCM). This is achieved by replacing the multipliers in generalized rational sampling rate converter (GRSRC) with codes derived from MCM algorithm. Using the existing generalized rational sampling rate converter structure, we achieved reduced computational complexity since the delay requirements are significantly reduced. However, in order to lower the cost of the hardware, we used a multiplierless approach. In addition, the area utilization of this modified structure has been seen to be significantly reduced in comparison to that of the unintegrated structure with a comparable trade-off in terms of the speed and power requirement. Simulink model is developed, and FPGA implementation is completed. It is seen that the computational performance and many other parameters are improved.
K. Gayathri, B. Krishna, A., and Dr. Navin Kumar, “Design of Generalized Rational Sampling Rate Converter Using Multiple Constant Multiplication”, in International Conference on Communication, Computing and Electronics Systems: Proceedings of ICCCES 2019, V. Bindhu, Chen, J., and Tavares, J. Manuel R., Eds. Singapore: Springer Singapore, 2020, pp. 455–466.