In Natural Language Processing applications, string matching is the main time-consuming operation. A dedicated co-processor for string matching that uses memory interleaving and parallel processing techniques can relieve the host CPU from this burden. This paper reports the FPGA design of such a system with m parallel matching units. It has been shown to improve the performance by a factor of nearly m, without increasing the chip area by more than 45% The time complexity of the proposed algorithm is O(log2 n), where n is the number of lexical entries. The memory used by the lexicon has been efficiently organized and the space saving achieved is about 67%.
V. S. Murty, Raj, P. C. Reghu, Raman, S., and Dr. P. P. Nikhil Raj, “Design of a high speed string matching co-processor for NLP”, in 16th International Conference on VLSI Design, 2003. Proceedings., 2003.