Cascaded Integrator Comb (CIC) filters are extensively used in Multirate signal processing as a filter for both decimation and interpolation processes. This paper analyzes optimized architecture and implementation aspects of decimator and interpolator using CIC filter and comparison between the results in hardware and simulations. The hardware is synthesized in FPGA and verified with Modelsim and Matlab simulation results. CIC filters function as efficient anti-aliasing filters before downsampling of signals in decimation process and as anti-imaging filters after upsampling of signals in interpolation process. This paper also discusses about pipelining, throughput and area reduction techniques and performance analysis with respect to the number of stages (N) and rate change factor (R) of the filter. © 2013 IEEE.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@62811dee ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@ad426c8 Through org.apache.xalan.xsltc.dom.DOMAdapter@6e3e1a05; Conference Code:97801
Dr. Ramesh Bhakthavatchalu, Karthika, V. S., Ramesh, L., and Aamani, B., “Design of optimized CIC decimator and interpolator in FPGA”, in Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013, Kerala, 2013, pp. 812-817.