General VLSI Cell placement has gone through different versions depending upon the particular applications. The area under modern challenges of VLSI desgin throw light on Power minimization, Thermal capacity and Area occupation. Thus Utility function, Renewal reward and Hypergraph setup are utilized in our discussion. A brief review is given in this paper. © 2005 - 2012 JATIT & LLS. All rights reserved.
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Ra Manikandan, Thiyagarajan, Mb, and Swaminathan, Pa, “Deterministic and probabilistic models on VLSI cell placement - A survey”, Journal of Theoretical and Applied Information Technology, vol. 37, pp. 39-45, 2012.