Publication Type:

Journal Article

Source:

Journal of Theoretical and Applied Information Technology, Volume 37, Number 1, p.39-45 (2012)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84858734995&partnerID=40&md5=57e95dd41c01356520ac3b0bc5e762a9

Keywords:

Cell placement, Hypergraph, Power minimization, Probabilistic models, Renewal reward process, Renewal-reward, Utility functions, VLSI Cell placement

Abstract:

General VLSI Cell placement has gone through different versions depending upon the particular applications. The area under modern challenges of VLSI desgin throw light on Power minimization, Thermal capacity and Area occupation. Thus Utility function, Renewal reward and Hypergraph setup are utilized in our discussion. A brief review is given in this paper. © 2005 - 2012 JATIT & LLS. All rights reserved.

Notes:

cited By (since 1996)0

Cite this Research Publication

Ra Manikandan, Thiyagarajan, Mb, and Swaminathan, Pa, “Deterministic and probabilistic models on VLSI cell placement - A survey”, Journal of Theoretical and Applied Information Technology, vol. 37, pp. 39-45, 2012.

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