A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented. This technique uses an offline algorithm to search and classify the random patterns based on the deterministic test patterns generated by the automatic test pattern generator (ATPG). The seed activated linear feedback shift register (LFSR) generates exhaustive test patterns which are applied on any design under test (DUT). The responses are received at the output of the scan chains in the DUT and they are compressed to produce a signature. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns than an arbitrary seed. Also, this technique helps to estimate the number of BIST test patterns to be generated to achieve specific fault coverage. Results on six ISCAS-89 designs with the help of Cadence Encounter true time 13.1 ATPG is shown. © 2014 IEEE.
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Dr. Ramesh Bhakthavatchalu, Krishnan, S., Vineeth, V., and Dr. Nirmala Devi M., “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.