Publication Type:

Conference Paper

Source:

18th International Symposium on VLSI Design and Test, VDAT 2014, IEEE Computer Society, Coimbatore (2014)

ISBN:

9781479950881

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84906690717&partnerID=40&md5=589b6a3124cd63a83580ec3a2e11769b

Keywords:

At-speed testing, ATPG, Design for testability, DFT, Integrated circuit testing, LBIST, LFSR, MISR, Random pattern, Scan chain, seed selection, Shift registers

Abstract:

A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented. This technique uses an offline algorithm to search and classify the random patterns based on the deterministic test patterns generated by the automatic test pattern generator (ATPG). The seed activated linear feedback shift register (LFSR) generates exhaustive test patterns which are applied on any design under test (DUT). The responses are received at the output of the scan chains in the DUT and they are compressed to produce a signature. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns than an arbitrary seed. Also, this technique helps to estimate the number of BIST test patterns to be generated to achieve specific fault coverage. Results on six ISCAS-89 designs with the help of Cadence Encounter true time 13.1 ATPG is shown. © 2014 IEEE.

Notes:

cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@1446db7c ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@37f3b44a Through org.apache.xalan.xsltc.dom.DOMAdapter@60c182f8; Conference Code:107214

Cite this Research Publication

R. Bhakthavatchalu, Krishnan, S., Vineeth, V., and M. Nirmala Devi, “Deterministic seed selection and pattern reduction in logic BIST”, in 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, 2014.