Publication Type:

Journal Article

Source:

International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 3, p.7537-7551 (2015)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84926435332&partnerID=40&md5=a0816a84131320ee2dc3fffb5bf71b3f

Abstract:

<p>A technique to select the proper seed and to reduce the number of test patterns generated in Logic Built in Self Test (BIST) is proposed. This paper explains the algorithm that can be used offline of BIST flow to search and classify the random patterns based on the deterministic test patterns generated by the Automatic Test Pattern Generator (ATPG). The seed activated Linear Feedback Shift Register (LFSR) generates exhaustive test patterns which are applied on any Circuit Under Test (CUT). The responses are received at the output of the scan chains in the CUT and they are compressed to produce a signature. This signature is compared with the expected golden signature to indicate the BIST status. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns compared to an arbitrary seed. This technique is well suited for any scan based sequential design. It is applied on ISCAS-89 designs with the help of Cadence Encounter Test Architect 13.1 tool. The results show that this method is comparable with similar methods. Possible limitations of this technique when employed in large designs and solutions are also suggested as future work. © Research India Publications.</p>

Notes:

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Cite this Research Publication

R. Bhakthavatchalu and M. Nirmala Devi, “Deterministic seed selection and pattern reduction in logic BIST”, International Journal of Applied Engineering Research, vol. 10, pp. 7537-7551, 2015.